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09005aef80b12a05 256mb_ddr2_1.fm - rev. d 7/04 en 1 ?2003 micron technology, inc. all rights reserved. 256mb: x4, x8, x16 ddr2 sdram ddr2 sdram mt47h64m4?16 meg x 4 x 4 mt47h32m8?8 meg x 8 x 4 mt47h16m16?4 meg x 16 x 4 for the latest data sheet, pl ease refer to the micron web site: http://www.micron. com/datasheets features ?v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v jedec standard 1.8v i/o (sstl_18-compatible) differential data strobe (dqs, dqs#) option four-bit prefetch architecture duplicate output strobe (rdqs) option for x8 configuration dll to align dq and dqs transitions with ck four internal banks for concurrent operation programmable cas latency (cl): 3 and 4 posted cas additive latency (al): 0, 1, 2, 3, and 4 write latency = read latency - 1 t ck programmable burst lengths: 4 or 8 adjustable data-output drive strength 64ms, 8,192-cycle refresh on-die termination (odt) options designation configuration 64 meg x 4 (16 meg x 4 x 4) 64m4 32 meg x 8 (8 meg x 8 x 4) 32m8 16 meg x 16 (4 meg x 16 x 4) 16m16 fbga package lead-free x4x8 60-ball fbga (8mm x 12mm) bp x16 84-ball fbga (8mm x 14)mm bg timing ? cycle time 5.0ns @ cl = 3 (ddr2-400) -5e 3.75ns @ cl = 4 (ddr2-533) -37e architecture 64 meg x 4 32 meg x 8 16 meg x 16 configuration 16 meg x 4 x 4 8 meg x 8 x 4 4 meg x 16 x 4 refresh count 8k 8k 8k row addressing 8k ( a0-a12 )8k ( a0-a12 )8k ( a0-a12 ) bank addressing 4 (ba0 - ba1) 4 (ba0 - ba1) 4 (ba0 - ba1) column addressing 2k ( a0-a9, a11 )1k ( a0-a9 ) 512 ( a0-a8 ) table 1: key timing parameters speed grade data rate (mhz) t rcd (ns) t rp (ns) t rc (ns) cl = 3 cl = 4 -5e 400 400 15 15 55 -37e 400 533 15 15 60
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_256mbtoc.fm - rev. d 7/04 en 2 ?2003 micron technology, inc. all rights reserved. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 fbga part marking decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 mode register (mr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 dll reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 write recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 extended mode register (emr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 dll enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 output drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 dqs# enable/disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 rdqs enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 output enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 on die termination (odt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 off-chip driver (ocd) impedance calibratio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 posted cas additive latency (al) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 extended mode register 2 (emr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 extended mode register 3 (emr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 deselect, nop, and load mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 load mode (lm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 bank/row activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 active command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 active operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 precharge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 self refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 power-down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 precharge power-down clock frequency change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 reset function (cke low anytime) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 odt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 ac and dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 input electrical characteristics and operat ing conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_256mbtoc.fm - rev. d 7/04 en 3 ?2003 micron technology, inc. all rights reserved. input slew rate derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 data slew rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 power and ground clamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 ac overshoot/undershoot specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 output electrical charac teristics and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 full strength pull-down driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 full strength pull-up driver characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 fbga package capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 i dd 7 conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_256mblof.fm - rev. d 7/04 en 4 ?2003 micron technology, inc. all rights reserved. list of figures figure 1: 256mb ddr2 part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 2: 84-ball fbga pin assignment (x16), 8mm x 14mm (top vi ew) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 3: 60-ball fbga pin assignment (x 4, x 8), 8mm x 12mm (t op view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: functional block diagram (64 meg x 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 5: functional block diagram (32 meg x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: functional block diagram (16 meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: ddr2 power-up and initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 8: mode register (mr) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 9: cas latency (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 10: extended mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 11: read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 12: write latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 13: extended mode register 2 (emr2) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 14: extended mode register 3 (emr3) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 15: active command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 16: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 17: example: meeting t rrd (min) and t rcd (min) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 18: read latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 19: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 20: nonconsecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 21: read interrupted by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 22: read to precharge bl = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 23: read to precharge bl = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 24: read to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 25: bank read ? without auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 26: bank read ? with auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 27: x4, x8 data output timing ? t dqsq, t qh, and data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 28: x16 data output timing ? t dqsq, t qh, and data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 29: data output timing ? t ac and t dqsck. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 30: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 31: write burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 32: consecutive write to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 33: nonconsecutive write to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 34: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 35: write interrupted by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 36: write to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 37: write to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 38: bank write?without auto precharg e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 39: bank write?with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 40: write?dm operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 41: data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 42: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 43: self refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 44: refresh mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 45: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 46: read to power-down entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 47: read with auto precharge to po wer-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 48: write to power-down entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 49: write with auto precharge to po wer-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 50: refresh command to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 51: active command to power-down en try . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 52: precharge command to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 53: load mode command to power-down entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 54: input clock frequency change during precharge po wer down mode . . . . . . . . . . . . . . . . . . . . . .64 figure 55: reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 56: odt timing for active or ?fast- exit? power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_256mblof.fm - rev. d 7/04 en 5 ?2003 micron technology, inc. all rights reserved. figure 57: odt timing for ?slow-exit? or pr echarge power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 figure 58: odt ?turn off? timings when ente ring power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 figure 59: odt ?turn-on? timing when enteri ng power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 60: odt ?turn-off? timing when exit ing power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 61: odt ?turn on? timing when exiting power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 figure 62: example temperature test point location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 figure 63: single-ended input signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 figure 64: differential input signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 figure 65: nominal slew rate for t is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 66: tangent line for t is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 67: nominal slew rate for t ih. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 figure 68: tangent line for t ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 figure 69: nominal slew rate for t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 figure 70: tangent line for t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 figure 71: nominal slew rate for t dh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 figure 72: tangent line for t dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 figure 73: ac input test signal waveform command/address pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 figure 74: ac input test signal waveform for data with dqs,dqs# (differential) . . . . . . . . . . . . . . . . . . . . . . . .84 figure 75: ac input test signal waveform for data with dqs (sin gle-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 76: ac input test signal waveform (differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 77: input clamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 figure 78: overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 figure 79: undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 figure 80: differential output signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 figure 81: output slew rate load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 figure 82: full strength pull-down characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 figure 83: full strength pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 figure 84: package drawing 60-ball (8mmx12mm) fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 85: package drawing 84-ball (8mmx14mm) fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. ddr2_256mblot.fm - rev. d 7/04 en 6 ?2003 micron technology, inc. all rights reserved. list of tables table 1: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: fbga ball descriptions 64 meg x 4, 32 meg x 8, 16 meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 3: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 4: truth table ? ddr2 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 5: truth table ? current state bank n - command to bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 6: truth table ? current state bank n - command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7: read using concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 8: write using concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 9: cke truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 10: odt timing for active and ?fast-ex it? power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 11: odt timing for ?slow-exit? and precharge power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 8 table 12: odt ?turn off? timings when entering power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 13: odt ?turn-on? timing when entering power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 0 table 14: odt ?turn-of? timing when exiting power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 table 15: odt ?turn on? timing when exiting power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 table 16: absolute maximum dc ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 table 17: recommended dc operating conditions (sstl_18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 18: odt dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 table 19: input dc logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 20: input ac logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 21: differential input logic levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 table 22: ac input test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 table 23: setup and hold time derating values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 table 24: t ds, t dh derating values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 25: input clamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 table 26: address and control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table 27: clock, data, strobe, and mask pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table 28: differential ac output parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table 29: output dc current drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 table 30: output characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 table 31: pulldown current (ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 32: pull-up current (ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table 33: input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 34: ddr2 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 35: general i dd parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 36: i dd 7 timing patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 table 37: ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 7 ?2003 micron technology, inc. all rights reserved. part numbers figure 1: 256mb ddr2 part numbers note: not all speeds and configurations are avail- able. fbga part marking decoder due to space limitations, fbga-packaged compo- nents have an abbreviated part marking that is differ- ent from the part number. micron's new fbga part marking decoder makes it easier to understand that part marking. visit the web site at www.micron.com/ decoder . general description the 256mb ddr2 sdram is a high-speed, cmos dynamic random-access memory containing 268,435,456 bits. it is internally configured as a quad- bank dram. the functional block diagrams of the 16 meg x 16, 32 meg x 8, and 64 meg x 4 devices, respec- tively are shown in the func tional description section. ball assignments for the 64 meg x 4 are shown in figure 2 and signal descriptions are shown in table 1. ball assignments for the 32 meg x 8 and 64 meg x 4 are shown in figure 2 and signal descriptions are shown in tabl e 2. the 256mb ddr2 sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architec ture is essentially a 4 n - prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb ddr2 sdram effectively consists of a single 4 n -bit-wide, one-clock-cycle data transf er at the internal dram core and four corresponding n -bit-wide, one-half- clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs, dqs#) is transmit- ted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram during reads and by the memory con- troller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 offering has two data strobes, one for the lower byte (ldqs, ldqs#) and one for the upper byte (udqs, udqs#). the 256mb ddr2 sdram operates from a differen- tial clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr2 sdram are burst-oriented; accesses st art at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr2 sdram provides for programmable read or write burst lengths of four or eight locations. ddr2 sdram supports interrupting a burst read of eight with another read, or a burst write of eight with another write. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard ddr sdrams, the pipelined, multibank architecture of ddr2 sdrams allows for concurrent operation, ther eby providing high, effec- tive bandwidth by hiding row precharge and activation time. a self refresh mode is provided, along with a power- saving power-down mode. all inputs are compatible with the jedec standard for sstl_18. all full drive-strength outputs are sstl_18-compatible. note: 1. the functionality and the timing specifica- tions discussed in this data sheet are for the dll-enabled mode of operation. 2. throughout the data sheet, the various fig- ures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq - configuration mt47h package speed configuration 64 meg x 4 32 meg x 8 16 meg x 16 64m4 32m8 16m16 package 60-ball 8 x 12 fbga lead-free 84-ball 8 x 14 fbga lead-free bp bg example part number: mt47h64m4ft-37e speed grade t ck = 5ns, cl = 3 t ck = 3.75ns, cl = 4 -5e -37e
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 8 ?2003 micron technology, inc. all rights reserved. collectively, unless specifically stated other- wise. additionally, the x16 is divided into two bytes, the lower byte and upper byte. for the lower byte (dq0 through dq7) dm refers to ldm and dqs refers to ldqs. for the upper byte (dq8 through dq15) dm refers to udm and dqs refers to udqs. 3. complete functionality is described throughout the document and any page or diagram may have been simplified to con- vey a topic and may not be inclusive of all requirements. 4. any specific requirement takes precedence over a general statement.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 9 ?2003 micron technology, inc. all rights reserved. figure 2: 84-ball fbga pin assignment (x16), 8mm x 14mm (top view) figure 3: 60-ball fbga pin assignment (x 4, x 8), 8mm x 12mm (top view) 1234 6789 5 v dd dq14 v dd q dq12 v dd dq6 v dd q dq4 v dd l rfu v ss v dd nc v ss q dq9 v ss q nc v ss q dq1 v ss q vref cke ba0 a10 a3 a7 a12 v ss udm v dd q dq11 v ss ldm v dd q dq3 v ss we# ba1 a1 a5 a9 rfu v ss q udqs v dd q dq10 v ss q ldqs v dd q dq2 v ss dl ras# cas# a2 a6 a11 rfu v dd q dq15 v dd q dq13 v dd q dq7 v dd q dq5 v dd odt v dd v ss nu/udqs# v ss q dq8 v ss q nu/ldqs# v ss q dq0 v ss q ck ck# cs# a0 a4 a8 rfu a b c d e f g h j k l m n p r 1234 6789 5 a b c d e f g h j k l v dd nf,dq6 v dd q nf,dq4 v dd l rfu v ss v dd nc,nu/rdqs# v ss q dq1 v ss q vref cke ba0 a10 a3 a7 a12 nu/dqs# v ss q dq0 v ss q ck ck# cs# a0 a4 a8 rfu v ss dm,dm/rdqs v dd q dq3 v ss we# ba1 a1 a5 a9 rfu v ss q dqs v dd q dq2 v ss dl ras# cas# a2 a6 a11 rfu v dd q nf,dq7 v dd q nf,dq5 v dd odt v dd v ss
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 10 ?2003 micron technology, inc. all rights reserved. table 2: fbga ball descriptions 64 me g x 4, 32 meg x 8, 16 meg x 16 x16 fbga ball assignment x4, x8 fbga ball assignment symbol type description k9 f9 odt input on-die termination: odt (registe red high) enables termination resistance internal to the ddr2 sd ram. when enabled, odt is only applied to each of the following pins: dq0?dq15, ldm, udm, ldqs, ldqs#, udqs, and udqs# for the x16; dq0-dq 7, dqs, dqs#, rdqs, rdqs#, and dm for the x8 ; dq0-dq3, dqs, dqs#, and dm for the x4. the odt input will be ig nored if disabled via the load mode command. j8, k8 e8, f8 ck, ck# input clock: ck and ck# are differenti al clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs/ dqs#) is referenced to the crossings of ck and ck#. k2 f2 cke input clock enable: cke (registered high) activates and cke (registered low) deactivates cloc king circuitry on the ddr2 sdram. the specific circuitry that is enabled/ disabled is dependent on the ddr2 sdram configuration and operating mode. cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down en try, power-down exit, output disable, and for self refresh entr y. cke is asynchronous for self refresh exit. input buffers (excludi ng ck, ck#, cke, and odt) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is an sstl_18 input but will detect a lvcmos low level once vdd is applied during first power- up. after vref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for prop er self-refresh operation v ref must be maintained. l8 g8 cs# input chip select: cs# enables (registere d low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple ranks. cs# is considered part of the command code. k7, l7, k3 f7, g7, f3 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. f3, b3 b3 ldm, udm input input data mask: dm is an input mask signal for write data. input data is masked when dm is samp led high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading is designed to match that of dq and dqs pins. ldm is dm for lower byte dq0? dq7 and udm is dm fo r upper byte dq8?dq15. l2, l3 g2, g3 ba0, ba1 input bank address inputs: ba0 and ba1 de fine to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 define which mode register including mr, emr, emr(2), and emr(3) is loaded during the load mode command.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 11 ?2003 micron technology, inc. all rights reserved. m8, m3, m7, n2, n8, n3, n7, p2, p8, p3, m2, p7, r2 h8, h3, h7, j2, j8, j3, j7, k2, k8, k3, h2, k7, l2 a0?a12 input address inputs: provide the row ad dress for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by ba0, ba1) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. g8, g2, h7, h3, h1, h9, f1, f9, c8, c2, d7, d3, d1, d9, b1, b9 ?dq0? dq15 i/o data input/output: bidirectio nal data bus for 16 meg x 16. ? c8, c2, d7, d3, d1, d9, b1, b9 dq0?dq7 i/o data input/output: bidirectional data bus for 32 meg x 8. ? c8, c2, d7, d3 dq0?dq3 i/o data input/output: bidirectional data bus for 64 meg x 4. b7, a8 ? udqs, udqs# i/o data strobe for upper byte: outp ut with read data, input with write data for source synchronou s operation. edge-aligned with read data, center-aligned with write data. udqs# is only used when differential data s trobe mode is enabled via the load mode command. f7, e8 ? ldqs, ldqs# i/o data strobe for lower byte: outp ut with read data, input with write data for source synchronou s operation. edge-aligned with read data, center-aligned with write data. ldqs# is only used when differential data s trobe mode is enabled via the load mode command. ? b7, a8 dqs, dqs# i/o data strobe: output with read data, input with write data for source synchronous operation. ed ge-aligned with read data, center aligned with write data. dqs# is only used when differential data strobe mode is enabled vi a the load mode command. ? b3, a2 rdqs, rdqs# output redundant data strobe for 32 meg x 8 only. rdqs is enabled/ disabled via the load mode co mmand to the extended mode register (emr). when rdqs is enabled, rdqs is output with read data only and is ignored during wr ite data. when rdqs is disabled, pin b3 becomes data mask (see dm pin). rdqs# is only used when rdqs is enabled and differential data strobe mode is enabled. a1, e1, j9, m9, r1 a1, e9, h9, l1 v dd supply power supply: 1.8v 0.1v j1 e1 v dd l supply dll power supply: 1.8v 0.1v a9, c1, c3, c7, c9, e9, g1, g3, g7, g9 a9, c1, c3, c7, c9 v dd q supply dq power supply: 1.8v 0.1v. isolated on the device for improved noise immunity. j2 e2 v ref supply sstl_18 reference voltage. a3, e3, j3, n1, p9 a3, e3, j1, k9 v ss supply ground. j7 e7 v ss dl supply dll ground. isolated on the device from v ss and v ss q. a7, b2, b8, d2, d8, e7, f2, f8, h2, h8, a7, b2, b8, d2, d8 v ss q supply dq ground. isolated on the device for improved noise immunity. table 2: fbga ball descriptions 64 me g x 4, 32 meg x 8, 16 meg x 16 x16 fbga ball assignment x4, x8 fbga ball assignment symbol type description
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 12 ?2003 micron technology, inc. all rights reserved. functional description the 256mb ddr2 sdram is a high-speed, cmos dynamic random-access memory containing 268,435,456 bits. the 256mb ddr2 sdram is inter- nally configured as a four-bank dram. the 256mb ddr2 sdram uses a double data rate architecture to achieve high-speed operation. the ddr2 architecture is essentially a 4 n -prefetch archi- tecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb ddr2 sdram consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and four corresponding n -bit- wide, one-half-clock-cycle data transfers at the i/o pins. prior to normal operation, the ddr2 sdram must be initialized. the following sections provide detailed information covering device initialization, register def- inition, command descriptions, and device operation. figure 4: functional block diagram (64 meg x 4) a2, e2 a2, b1, b9, d1, d9 nc ? no connect: these pins should be left unconnected. d1, d9, b1, b9 nf - no function: these pins are used as dq4-dq7 on the 32 meg x 8, but are nf (no function) on the 16 meg x 16 configuration. a8, e8 a2, a8 nu ? not used: if emr[e10] = 0, a8 and e8 are udqs# and ldqs#. if emr[e10] = 1, then a8 and e8 are not used. l1, r3, r7, r8 g1, l3, l7, l8 rfu ? reserved for future use; bank addr ess bit ba2(l1) for 1gb, 2gb, and 4gb densities. row address bits a13(r8), a14(r3) and a15(r7) for higher densities. table 2: fbga ball descriptions 64 me g x 4, 32 meg x 8, 16 meg x 16 x16 fbga ball assignment x4, x8 fbga ball assignment symbol type description 13 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch mode registers 11 command decode a0-a12, ba0, ba1 cke 13 address register 15 512 (x16) 8,192 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 512 x 16) bank0 row- address latch & decoder 8,192 sense amplifiers bank control logic 15 bank1 bank2 bank3 13 9 2 2 refresh counter 4 4 4 2 rcvrs 16 16 16 ck out data dqs, dqs# ck, ck# col0,col1 col0,col1 ck in drvrs dll mux dqs generator 4 4 4 4 4 dq0 - dq3 dqs, dqs # 2 read latch write fifo & drivers data 4 4 4 4 16 1 1 1 1 mask 1 1 1 1 1 4 4 4 2 bank1 bank2 bank3 input registers dm vddq r1 r1 r2 r2 sw1 sw2 vssq r1 r1 r2 r2 sw1 sw2 r1 r1 r2 r2 sw1 sw2 odt sw1 sw2 odt control internal ck, ck#
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 13 ?2003 micron technology, inc. all rights reserved. figure 5: functional block diagram (32 meg x 8) figure 6: functional bl ock diagram (16 meg x 16) 13 row- address mux control logic column- address counter/ latch mode registers 10 command decode 0 ?a12, 0 , ba1 13 address register 15 256 (x32) 8,192 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 256 x 32) bank0 row- address latch & decoder 8,192 sense amplifiers bank control logic 15 bank1 bank2 bank3 13 8 2 2 refresh counter 8 8 8 2 rcvrs 32 32 32 ck out data dqs, dqs# internal ck, ck# ck,ck# col0,col1 col0,col1 ck in drvrs dll mux dqs generator 8 8 8 8 8 dq0?dq7 dqs, dqs# 2 read latch write fifo & drivers data 8 8 8 8 32 1 1 1 1 mask 1 1 1 1 1 4 8 8 2 bank1 bank2 bank3 input registers dm rdqs# v dd q r1 r1 r2 r2 sw1 sw2 vssq r1 r1 r2 r2 sw1 sw2 r1 r1 r2 r2 sw1 sw2 sw1 sw2 odt control ras# cas# ck cs# we# ck# cke odt rdqs 13 row- address mux control logic column- address counter/ latch mode registers 9 a0?a12, ba0, ba1 13 address register 15 128 (x64) 8,192 i/o gating dm mask logic column decoder bank0 memory array (8,192 x 128 x 64) bank0 row- address latch & decoder 8,192 sense amplifiers bank control logic 15 bank1 bank2 bank3 13 7 2 2 refresh counter 16 16 16 4 rcvrs 64 64 64 ck out data udqs, udqs# ldqs, ldqs# internal ck, ck# ck,ck# col0,col1 col0,col1 ck in dll mux dqs generator 16 16 16 16 16 udqs, udqs# ldqs, ldqs# 4 read latch write fifo & drivers data 16 16 16 16 64 2 2 2 2 mask 2 2 2 2 2 8 16 16 2 bank1 bank2 bank3 input registers udm, ldm dq0?dq15 v dd q r1 r1 r2 r2 sw1 sw2 vssq r1 r1 r2 r2 sw1 sw2 r1 r1 r2 r2 sw1 sw2 sw1 sw2 odt control ras# cas# ck cs# we# ck# command decode cke odt drvrs
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 14 ?2003 micron technology, inc. all rights reserved. initialization the following sequence is required for power-up and initialization and is shown in figure 7. 1. apply power; if cke is maintained below 0.2* v dd q, outputs remain disabled. to guarantee r tt (odt resistance) is off, v ref must be valid and a low level must be applied to the odt pin (all other inputs may be undefined). the time from when v dd first starts to power-up to the completion of v dd q must be equal to or less than 10ms. at least one of the following two sets of conditions (a or b) must be met: a .c ondition s et a v dd , v dd l and v dd q are driven from a single power converter output v tt is limited to 0.95v max v ref tracks v dd q/2. b .c ondition s et b apply v dd before or at the same time as v dd l. apply v dd l before or at the same time as v dd q. apply v dd q before or at the same time as v tt and v ref . the voltage difference between any v dd supply can not exceed 0.5v. for a minimum of 200 s after stable power and clock (ck, ck#), apply nop or deselect commands and take cke high. 2. wait a minimum of 400ns, then issue a pre- charge all command. 3. issue an load mode command to the emr(2) register. (to issue an emr(2) command, provide low to ba0, provide high to ba1.) 4. issue a load mode command to the emr(3) register. (to issue an emr(3) command, provide high to ba0 and ba1.) 5. issue an load mode command to the emr reg- ister to enable dll. to issue a dll enable com- mand, provide low to ba1 and a0, provide high to ba0. bits e7, e8, and e9 must all be set to 0. 6. issue a load mode command for dll reset. 200 cycles of clock input is required to lock the dll. (to issue a dll reset, provide high to a8 and provide low to ba1 and ba0.) cke must be high the entire time. 7. issue precharge all command. 8. issue two or more refresh commands. 9. issue a load mode command with low to a8 to initialize device operation (i.e., to program oper- ating parameters without resetting the dll). 10. issue a load mode command to the emr to enable ocd default by setting bits e7, e8, and e9 to 1 and set all other desired parameters. 11. issue a load mode command to the emr to enable ocd exit by setting bits e7, e8, and e9 to 0 and set all other desired parameters. 12. the ddr2 sdram is now intialized and ready for normal operation 200 clocks after dll reset in step 6.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 15 ?2003 micron technology, inc. all rights reserved. figure 7: ddr2 power-up and initialization note: 1. v tt is not applied directly to the device ; however, t vtd should be greater than or equal to zero to avoid device latch-up. the time from when v dd first starts to power-up to the completion of v dd q must be equal to or less than 10ms. one of the following two conditions (a or b) must be met: a) v dd , v dd l, and v dd q are driven from a single power converter output. v tt may be 0.95v maximu m during power up. v ref tracks v dd q/2. b) apply v dd before or at the same time as v dd l. apply v dd l before or at the same time as v dd q. apply v dd q before or at the same time as v tt and v ref . the voltage difference between any v dd supply can not exceed 0.5v. 2. either a nop or deselect command may be applied. 3. 200 cycles of clock (ck, ck#) are re quired before a read command can be issu ed. cke must be high the entire time. 4. two or more refresh commands are required. 5. bits e7, e8, and e9 must all be se t to 0 with all other operating parameters of emrs set as required. 6. pre = precharge command, lm = load mode command, ref = refresh command, act = active command, ra = row address, ba = bank address. 7. dm represents dm for x4, x8 configuration and udm, ldm for x16 configuration. dqs re presents dqs, dqs#, udqs, udqs#, ldqs, ldqs#, rdqs, rdqs# for the appropriate configuration (x4, x8, x16). dq represents dq0?dq3 for x4, dq0?dq7 for x8, and dq0?dq15 for x16. 8. cke pin uses lvcmos input levels prior to state t0. after state t0 , cke pin uses sstl_18 input levels. 9. address represents a12-a0 for x4, x8, and a12-a0 for x16, ba0-ba1. a10 should be high at states tb0 and tg0 to ensure a precharge (all ba nks) command is issued. 10. bits e7, e8, and e9 must be set to 1 to set ocd default. 11. bits e7, e8, and e9 must be set to 0 to set ocd exit and all other operating parameters of emrs set as required. t vtd 1 cke rtt power-up: v dd and stable clock (ck, ck#) t = 200s (min) high-z dm 7 dqs 7 high-z address 10 ck ck# t cl v tt 1 v ref v ddl v dd q command 6 nop 2 pre t0 ta0 don?t care t cl t ck v dd odt dq 7 high-z t = 400ns (min) tb0 200 cycles of ck 3 emr with dll enable 5 mr with dll reset t mrd t mrd tt rfc t rfc code 9 lm pre lm 5 ref 4 ref 4 lm 10 code 10 code 10 code 10 tg0 th0 ti0 tj0 mr w/o dll resett emr with ocd default t mrd t mrd t mrd tk0 tl0 tm0 te0 tf0 emr(2) 9 emr(3) 9 t mrd t mrd lm 9 lm 9 code 10 code 10 code 10 t rp a tc0 td0 lvcmos low level 8 sstl_18 low level 8 valid 3 valid indicates a break in time scale rp a lm 11 code 9 emr with ocd exit lm 12 code 9 normal operation
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 16 ?2003 micron technology, inc. all rights reserved. mode register (mr) the mode register is used to define the specific mode of operation of the ddr2 sdram. this defini- tion includes the selection of a burst length, burst type, cas latency, operating mode, dll reset, write recov- ery, and power-down mode as shown in figure 8. con- tents of the mode register can be altered by re- executing the load mode (lm) command. if the user chooses to modify only a subset of the mr vari- ables, all variables (m0? m14) must be programmed when the load mode command is issued. the mode register is programmed via the lm com- mand (bits ba1-ba0 = 0, 0) and other bits (m12 - m0) will retain the stored information until it is pro- grammed again or the device loses power (except for bit m8, which is self-clearing). reprogramming the mode register will not alte r the contents of the mem- ory array, provided it is performed correctly. the load mode command can only be issued (or reissued) when all banks are in the precharged state. the controller must wait the specified time t mrd before initiating any subseq uent operations such as an active command. violating either of these require- ments will result in unspecified operation. burst length burst length is defined by bits m0?m3 as shown in figure 8. read and write accesses to the ddr2 sdram are burst-oriented, with the burst length being pro- grammable to either four or eight. the burst length determines the maximum number of column loca- tions that can be accessed for a given read or write command. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a2?a i when the burst length is set to four and by a3?a i when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least signifi- cant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. figure 8: mode register (mr) definition burst type accesses within a given burst may be programmed to be either sequential or interleaved. the burst type is selected via bit m3 as shown in figure 8. the ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address as shown in table 3. ddr2 sdram supports 4-bit burst and 8-bit burst modes only. for 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based. burst length cas# latency bt pd a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 burst length reserved reserved 4 8 reserved reserved reserved reserved m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 0 1 burst type sequential interleaved m3 cas latency reserved reserved 2 3 4 5 reserved reserved m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 0 1 mode normal test m7 14 dll tm 0 1 dll reset no yes m8 write recovery reserved 2 3 4 5 6 reserved reserved m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1 wr mr 0 1 0 1 mode register mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) m14 0 0 1 1 0 1 pd mode fast exit (normal) slow exit (low power) m12 m13
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 17 ?2003 micron technology, inc. all rights reserved. operating mode the normal operating mode is selected by issuing a load mode command with bit m7 set to zero, and all other bits set to the desired values as shown in figure 8. when bit m7 is ?1,? no other bits of the mode register are programmed. programming bit m7 to ?1? places the ddr2 sdram into a test mode that is only used by the manufacturer and should not be used. no operation or functionality is guaranteed if m7 bit is ?1.? dll reset dll reset is defined by bit m8 as shown in figure 8. programming bit m8 to ?1? wi ll activate the dll reset function. bit m8 is self-clearing, meaning it returns back to a value of ?0? after the dll reset function has been issued. anytime the dll reset function is used, 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be syn- chronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters. write recovery write recovery (wr) time is defined by bits m9?m11 as shown in figure 8. the wr register is used by the ddr2 sdram during write with auto precharge operation. during write with auto precharge operation, the ddr2 sdram delays the internal auto precharge operation by wr clocks (programmed in bits m9?m11) from the last data burst. an example of write with auto precharge is shown in figure 26 on page 30. write recovery (wr) values of 2, 3, 4, 5, or 6 clocks may be used for programming bits m9?m11. the user is required to program the value of write recovery, which is calculated by dividing t wr (in ns) by t ck (in ns) and rounding up a noninteger value to the next integer; wr [cycles] = t wr [ns] / t ck [ns]. reserved states should not be used as unknown operation or incompatibility with future versions may result. power-down mode active power-down (pd) mode is defined by bit m12 as shown in figure 8. pd mode allows the user to determine the active power-down mode, which deter- mines performance vs. power savings. pd mode bit m12 does not apply to precharge power-down mode. when bit m12 = 0, standard active power-down mode or ?fast-exit? active power-down mode is enabled. the t xard parameter is used for ?fast-exit? active power-down exit timing. the dll is expected to be enabled and running during this mode. when bit m12 = 1, a lower power active power-down mode or ?slow-exit? active power-down mode is enabled. the t xards parameter is used for ?slow-exit? active power-down exit timing. the dll can be enabled, but ?frozen? during active power-down mode since the exit-to-read co mmand timing is relaxed. the power difference expected between pd ?normal? and pd ?low-power? mode is defined in the i dd table. cas latency (cl) the cas latency (cl) is defined by bits m4?m6 as shown in figure 8. cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the cas latency can be set to 3 or 4 clocks. cas latency of 2 or 5 clocks are jedec optional features and may be enabled in future speed grades. ddr2 sdram does not support any half clock latencies. reserved states should not be used as unknown operation or incom- patibility with future versions may result. ddr2 sdram also supports a feature called posted cas additive latency (al). this feature allows the read command to be issued prior to t rcd(min) by delaying the internal command to the ddr2 sdram by al clocks. the al feature is described in more detail in the extended mode register (emr) and operational sections. table 3: burst definition burst length starting column address (a2, a1, a0) order of acce sses within a burst burst type = sequential burst type = interleaved 4 0 0 0 0,1,2,3 0,1,2,3 0 0 1 1,2,3,0 1,0,3,2 0 1 0 2,3,0,1 2,3,0,1 0 1 1 3,0,1,2 3,2,1,0 8 0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 0 0 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 0 1 0 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 0 1 1 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 1 0 1 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2 1 1 0 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1 1 1 1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 18 ?2003 micron technology, inc. all rights reserved. examples of cl = 3 and cl = 4 are shown in figure 9; both assume al = 0. if a read command is registered at clock edge n , and the cas latency is m clocks, the data will be available nomi nally coincident with clock edge n + m (this assumes al = 0). figure 9: cas latency (cl) d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# cl = 3 (al = 0) read burst length = 4 posted cas# additive latency (al) = 0 shown with nominal t ac, t dqsck, and t dqsq t0 t1 t2 don?t care transitioning data nop nop nop d out n t3 t4 t5 nop nop t6 nop d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# cl = 4 (al = 0) read t0 t1 t2 nop nop nop d out n t3 t4 t5 nop nop t6 nop
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 19 ?2003 micron technology, inc. all rights reserved. extended mode register (emr) the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable, output drive strength, odt (r tt ), posted cas additive latency (al), off-chip driver impedance calibration (ocd), dqs# enable/disable, rdqs/rdqs# enable/disable, and output disable/enable. these functions are controlled via the bits shown in figure 10. the extended mode register is programmed via the load mode (lm) command and will retain the stored infor- mation until it is programmed again or the device loses power. reprogramming the extended mode reg- ister will not alter the contents of the memory array, provided it is performed correctly. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent op eration. violating either of these requirements could result in unspecified opera- tion. figure 10: extended mode register definition dll enable/disable the dll may be enabled or disabled by program- ming bit e0 during the load mode command as shown in figure 10. the dll must be enabled for nor- mal operation. dll enable is required during power- up initialization and upon returning to normal opera- tion after having disabled the dll for the purpose of debugging or evaluation. enabling the dll should always be followed by resetting the dll using a load mode command. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled and reset upon exit of self refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. fail- ing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters. output drive strength the output drive strength is defined by bit e1 as shown in figure 10. the normal drive strength for all outputs are specified to be sstl_18. programming bit e1 = 0 selects normal (100 percent) drive strength for all outputs. selecting a reduced drive strength option (bit e1 = 1) will reduce all outputs to approximately 60 percent of the sstl_18 drive strength. this option is intended for the support of the lighter load and/or point-to-point environments. dqs# enable/disable the dqs# enable function is defined by bit e10. when enabled (bit e10 = 0), dqs# is the complement of the differential data strobe pair dqs/dqs#. when disabled (bit e10 = 1), dqs is used in a single-ended mode and the dqs# pin is disabled. this function is also used to enable/disable rdqs#. if rdqs is enabled (e11 = 1) and dqs# is enabled (e10 = 0), then both dqs# and rdqs# will be enabled. rdqs enable/disable the rdqs enable function is defined by bit e11 as shown in figure 10. this feature is only applicable to the x8 configuration. when enabled (e11 = 1), rdqs is identical in function and timing to data strobe dqs during a read. during a write operation, rdqs is ignored by the ddr2 sdram. dll posted cas# r tt out a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 0 1 output drive strength 100% 60% e1 posted cas# additive latency (al) 0 1 2 3 4 reserved reserved reserved e3 0 1 0 1 0 1 0 1 e4 0 0 1 1 0 0 1 1 e5 0 0 0 0 1 1 1 1 0 1 dll enable enable (normal) disable (test/debug) e0 14 0 1 rdqs enable no yes e11 ocd program ods r tt dqs# 0 1 dqs# enable enable disable e10 rdqs r tt (nominal) r tt disabled 75 ohm 150 ohm reserved e2 0 1 0 1 e6 0 0 1 1 0 1 outputs enabled disabled e12 0 1 0 1 mode register mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) m14 0 0 1 1 m13 emr ocd operation ocd exit reserved reserved reserved ocd default e7 0 1 0 0 1 e8 0 0 1 0 1 e9 0 0 0 1 1
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 20 ?2003 micron technology, inc. all rights reserved. output enable/disable the output enable function is defined by bit e12 as shown in figure 10. when enabled (e12 = 0), all out- puts (dqs, dqs, dqs#, rdqs, rdqs#) function nor- mally. when disabled (e12 = 1), all ddr2 sdram outputs (dqs, dqs, dqs#, rdqs, rdqs#) are disabled removing output buffer current. the output disable feature is intended to be used during i dd characteriza- tion of read current. on die termination (odt) odt effective resistance r tt ( eff ) is defined by bits e2 and e6 of the emr as shown in figure 10. the odt feature is designed to improve signal integrity of the memory channel by allowing the ddr2 sdram con- troller to independently turn on/off odt for any or all devices. r tt effective resistance values of 75 ? and 150 ? are selectable and apply to each dq, dqs/dqs#, rdqs/rdqs#, udqs/udqs#, ldqs/ldqs#, dm, and udm/ldm signals. a func tional representation of odt is shown in block diagrams in ?functional description? on page 12. bits (e6, e2) determine what odt resistance is enabled by turning on/off ?sw1? or ?sw2?. the odt effective resistance value is selected by enabling switch ?sw1,? which enables all ?r1? values that are 150 ? each, enabling an effective resistance of 75 ? ( r tt 1( eff ) = ?r1? / 2). similarly, if ?sw2? is enabled, all ?r2? values that are 300 ? each, enable an effective odt resistance of 150 ? ( r tt 2( eff ) = ?r2?/2). reserved states should not be used, as unknown operation or incompatibility with future versions may result. the odt control pin is used to determine when r tt ( eff ) is turned on and off, assuming odt has been enabled via bits e2 and e6 of the emr. the odt fea- ture and odt input pin are only used during active, active power-down (both fast-exit and slow-exit modes), and precharge power-down modes of opera- tion. if self refresh operation is used, r tt ( eff ) should always be disabled and the odt input pin is disabled by the ddr2 sdram. during power-up and initialization of the ddr2 sdram, odt should be dis- abled until the emr command is issued to enable the odt feature, at which point the odt pin will deter- mine the r tt ( eff ) value. see ?odt timing? on page 9 for odt timing diagrams.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 21 ?2003 micron technology, inc. all rights reserved. off-chip driver (ocd) impedance calibration the ocd function is no longer supported and must be set to the default state. see ?initialization? on page 14 to propertly set ocd defaults. posted cas additive latency (al) posted cas additive latency (al) is supported to make the command and data bus efficient for sustain- able bandwidths in ddr2 sdram. bits e3?e5 define the value of al as shown in figure 10. bits e3?e5 allow the user to program the ddr2 sdram with a cas# additive latency of 0, 1, 2, 3, or 4 clocks. reserved states should not be used as unknown operation or incom- patibility with future versions may result. in this operation, the dd r2 sdram allows a read or write command to be issued prior to t rcd (min) with the requirement that al t rcd(min). a typical application using this feature would set al = t rcd (min) - 1 x t ck. the read or write command is held for the time of the additive latency (al) before it is issued internally to the ddr2 sdram device. read latency (rl) is controlled by the sum of the posted cas additive latency (al) and cas latency (cl); rl = al + cl. write latency (wl) is equal to read latency minus one clock; wl = al + cl - 1 x t ck. an example of a read latency is shown in figure 11. an example of a write latency is shown in figure 12. figure 11: read latency figure 12: write latency d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# al = 2 active n burst length = 4 shown with nominal t ac, t dqsck, and t dqsq t0 t1 t2 don?t care transitioning data read n nop nop d out n t3 t4 t5 nop t6 nop t7 t8 nop nop cl = 3 rl = 5 cas# latency (cl) = 3 additive latency (al) = 2 read latency (rl) = al + cl = 5 t rcd (min) nop ck ck# command dq dqs, dqs# active n burst length = 4 t0 t1 t2 don?t care transitioning data nop nop t3 t4 t5 nop write n t6 nop d in n + 3 d in n + 2 d in n + 1 wl = al + cl - 1 = 4 t7 nop d in n cas# latency (cl) = 3 additive latency (al) = 2 write latency = al + cl -1 = 4 t rcd (min) nop al = 2 cl - 1 = 2
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 22 ?2003 micron technology, inc. all rights reserved. extended mode register 2 (emr2) the extended mode register 2 (emr2) controls functions beyond those cont rolled by the mode regis- ter. currently all bits in em r2 are reserved as shown in figure 13. the emr2 is programmed via the load mode command and will retain the stored informa- tion until it is programmed again or the device loses power. reprogramming the extended mode register will not alter the contents of the memory array, pro- vided it is performed correctly. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent op eration. violating either of these requirements could result in unspecified oper- ation. figure 13: extended mode register 2 (emr2) definition extended mode register 3 (emr3) the extended mode register 3 (emr3) controls functions beyond those controlled by the mode regis- ter. currently all bits in emr3 are reserved as shown in figure 14. the emr3 is programmed via the load mode command and will retain the stored informa- tion until it is programmed again or the device loses power. reprogramming the extended mode register will not alter the contents of the memory array, pro- vided it is performed correctly. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t mrd before initiating any subsequent operation. violating either of these requirements could result in unspecified opera- tion. figure 14: extende d mode register 3 (emr3) definition a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 * e12 (a12)?e0 (a0) are reserved for future use and must all be programmed to '0.' 14 0 1 0 1 mode register mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) e14 0 0 1 1 e13 emr(2) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 976543 8210 a10 a12 a11 ba0 ba1 10 11 12 13 * e12 (a12)?e0 (a0) are reserved for future use and must all be programmed to '0.' 14 0 1 0 1 mode register mode register (mr) extended mode register (emr) extended mode register (emr2) extended mode register (emr3) e14 0 0 1 1 e13 emr(3) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 23 ?2003 micron technology, inc. all rights reserved. command truth tables the following tables provide a quick reference of ddr2 sdram available commands, including cke power-down modes, and bank-to-bank commands. note: 1. all ddr2 sdram commands are defined by states of cs#, ra s#, cas#, we#, and cke at the rising edge of the clock. 2. bank addresses (ba) ba1-ba0 determine which bank is to be operated upon. ba during a load mode command selects which mode register is programmed. 3. burst reads or writes at bl = 4 cannot be terminated or interrupted. see sections ?r ead interrupted by a read? and ?write interrupted by a write? fo r other restrictions and details. 4. the power down mode does not perform any refresh operations. the duration of power-down is therefore limited by the refresh requirements outlined in the ac parametric section. 5. the state of odt does not affect the state s described in this table. the odt function is not avai lable during self refresh. see the odt section for details. 6. ?x? means ?h or l? (but a defined logic level). 7. self refresh exit is asynchronous. table 4: truth table ? ddr2 commands notes: 1, 5, and 6 appl y to the entire table. function cke cs# ras# cas# we# ba1 ba0 a12 a11 a10 a9?a0 notes previous cycle current cycle load mode h h l l l l ba op code 2 refresh hhlllhxxxx self refresh entry hllllhxxxx self refresh exit lh hx xx xxxx 7 lhhh single bank precharge hhllhlbaxlx2 all banks precharge hhllhlxxhx bank activate h h l l h h ba row address write hhlhllba column address l column address 2, 3 write with auto precharge hhlhllba column address h column address 2, 3 read hhlhlhba column address l column address 2, 3 read with auto precharge hhlhlhba column address h column address 2, 3 no operation hxlhhhxxxx device deselect hxhxxxxxxx power-down entry hl hx xx xxxx 4 lhhh power-down exit lh hx xx xxxx 4 lhhh
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 24 ?2003 micron technology, inc. all rights reserved. note: 1. this table applies when cke n - 1 was high and cke n is high (see table 5) and after t xsnr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted (i.e., the cu rrent state is for a specific ba nk and the commands shown are those allowed to be issued to that bank when in th at state). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no reg- ister accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated. 4. the following states must not be inte rrupted by a command issued to the same bank. deselect or nop commands, or allowable commands to the other bank, should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and table 5, and according to table 6. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the ?row active? state. read with auto precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write with auto precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an refresh comm and and ends when t rfc is met. once t rfc is met, the ddr2 sdram will be in the all banks idle state. accessing mode register: starts with registra tion of a load mode command and ends when t mrd has been met. once t mrd is met, the ddr2 sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not sh own are illegal or reserved. 7. not bank-specific; requires that all banks are idle, a nd bursts are not in progress. 8. may or may not be bank-specific; if mu ltiple banks are to be precharged, each must be in a valid state for precharging. table 5: truth table ? current state bank n - command to bank n notes: 1?6; notes appear below and on next page. current state cs# ras# cas# we# command/action notes any hxxx deselect (nop/continue previous operation) l hhh no operation (nop/continue previous operation) idle l l h h active (select and activate row) lllh refresh 7 llll load mode 7 row activelhlh read (select column and start read burst) 9 lhl l write (select column an d start write burst) 9 llhl precharge (deactivate row in bank or banks) 8 read (auto- precharge disabled lhlh read (select column and start new read burst) 9 lhl l write (select column and start write burst) 9, 11 llhl precharge ( start precharge) 8 write (auto- precharge disabled) lhlh read (select column and start read burst) 9, 10 lhl l write (select column and start new write burst) 9 llhl precharge (start precharge) 8, 10
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 25 ?2003 micron technology, inc. all rights reserved. 9. reads or writes listed in the command/action column in clude reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 10. requires appropriate dm masking. 11. a write command may be applied a fter the completion of the read burst.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 26 ?2003 micron technology, inc. all rights reserved. note: 1. this table ap plies when cke n - 1 was high and cke n is high (see truth table 2) and after t xsnr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, exce pt where noted (i.e., the current state is for bank n and the com- mands shown are those allowed to be issued to bank m , assuming that bank m is in such a state that the given com- mand is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the ba nk has been activated, and t rcd has been met. no data bursts/accesses and no reg- ister accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated. read with auto precharge enab led: see following text ? 3a write with auto precharge enab led: see following text ? 3a 3a.the read with auto precharge enable d or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. fo r read with auto precharge, the precharge period is defined as if the same burst was exec uted with auto precharge disabled and then follow ed with the earliest pos- sible precharge command that still access es all of the data in the burst. fo r write with auto precharge, the pre- charge period begins when t wr ends, with t wr measured as if auto precharg e was disabled. the access period starts with registration of the command an d ends where the pr echarge period (or t rp) begins. this device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled any command to other ba nks is allowed, as long as that command does not interrupt the read or write data transf er already in process. in either ca se, all other relate d limitations apply (e.g., contention between read data and write data must be avoided). table 6: truth table ? current state bank n - command to bank m notes: 1?6; notes appear below and on next page. current state cs# ras# cas# we# command/action notes any hxxx deselect (nop/continu e previous operation) lhhh no operation (nop/conti nue previous operation) idle xxxx any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled llhh active (select and activate row) lhlh read (select column and start new read burst) 7 lhl l write (select column and start write burst) 7, 9 llhl precharge write (auto precharge disabled.) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 8 lhl l write (select column and start new write burst) 7 llhl precharge read (with auto- precharge) llhh active (select and activate row) lhlh read (select column and start new read burst) 7, 3a lhl l write (select column and start write burst) 7, 9, 3a llhl precharge write (with auto- precharge) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 3a lhl l write (select column and start new write burst) 7, 3a llhl precharge
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 27 ?2003 micron technology, inc. all rights reserved. 3b.the minimum delay from a read or write command with auto precha rge enabled, to a command to a differ- ent bank is summarized below. 4. refresh and load mode commands may on ly be issued when all banks are idle. 5. not used. 6. all states and sequences not sh own are illegal or reserved. 7. reads or writes listed in the command/action column in clude reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied a fter the completion of the read burst. 10. t wtr is defined as min (2 or t wtr/ t ck rounded up to the next integer). cl = cas latency; bl = bust length; wl = write latency from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units write with auto precharge read or read w/ap (cl - 1) + (bl / 2) + t wtr t ck write or write w/ap (bl / 2) t ck precharge or active 1 t ck read with auto precharge read or read w/ap (bl / 2) t ck write or write w/ap (bl / 2) + 2 t ck precharge or active 1 t ck
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 28 ?2003 micron technology, inc. all rights reserved. deselect, nop, and load mode commands deselect the deselect function (cs# high) prevents new commands from being executed by the ddr2 sdram. the ddr2 sdram is effectively deselected. opera- tions already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected ddr2 sdram to perform a nop (cs# is low; ras#, cas#, an d we are high). this pre- vents unwanted commands from being registered dur- ing idle or wait states. operations already in progress are not affected. load mode (lm) the mode registers are loaded via inputs ba1-ba0 and a12 ? a0 for x4 and x8, and a12 - a0 for x16 config- urations. ba1-ba0 determine which mode register will be programmed. see ?mode register (mr)? on page 11. the load mode command can only be issued when all banks are idle, and a subsequent exe- cutable command cannot be issued until t mrd is met.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 29 ?2003 micron technology, inc. all rights reserved. bank/row activation active command the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba1-ba0 inputs selects the bank, and the address provided on inputs a12 ? a0 for x4 and x8, and a12 - a0 for x16 selects the row. this row remains active (or open) for access es until a precharge com- mand is issued to that bank. a precharge command must be issued before opening a different row in the same bank. active operation before any read or write commands can be issued to a bank within the ddr2 sdram, a row in that bank must be ?opened? (activated). this is accom- plished via the active command, which selects both the bank and the row to be activated, as shown in figure 15. figure 15: active command after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to dete rmine the earliest clock edge after the active command on which a read or write command can be entered. the same procedure is used to convert other sp ecification limits from time units to clock cycles. for example, a t rcd(min) speci- fication of 20ns with a 266 mhz clock ( t ck = 3.75ns) results in 5.3 clocks rounded up to 6. this is reflected in figure 17, which covers any case where 5 < t rcd (min) / t ck 6. figure 17 also shows the case for t rrd where 2 < t rrd (min) / t ck 3. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the mini- mum time interval between successive active com- mands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access over- head. the minimum time interval between successive active commands to different banks is defined by t rrd. don?t care ck ck# cs# ras# cas# we# cke row bank address bank address
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 30 ?2003 micron technology, inc. all rights reserved. reads read command the read command is used to initiate a burst read access to an active row. the value on the ba1-ba0 inputs selects the bank, and the address provided on inputs a0? i (where i = a9 for x16, a9 for x8, or a9, a11 for x4) selects the starting column location. the value on input a10 determines whether or not auto pre- charge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precha rge is not selected, the row will remain open for subsequent accesses. read operation read bursts are initiated with a read command, as shown in figure 16. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. if auto precharge is disabled, the row will be left open after the completion of the burst. during read bursts, the valid data-out element from the starting column address will be available read latency (rl) clocks la ter. read latency (rl) is defined as the sum of posted cas additive latency (al) and cas latency (cl); rl = al + cl. the value for al and cl are programmable via the mr and emr com- mands, respectively. each subsequent data-out ele- ment will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of ck and ck#). figure 18 shows examples of read latency based on different al and cl settings. figure 16: read command figure 17: example: meeting t rrd (min) and t rcd (min) don?t care ck ck# cs# ras# cas# we# cke col bank address bank address auto precharge enable disable a10 command don?t care t1 t0 t2 t3 t4 t5 t6 t7 t rrd row row col bank x bank y bank y nop act nop nop act nop nop rd/wr t rcd ba0, ba1 ck# address ck t8 t9 nop nop
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 31 ?2003 micron technology, inc. all rights reserved. figure 18: read latency note: 1. do n = data-out from column n . 2. burst length = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. shown with nominal t ac, t dqsck, and t dqsq. read nop nop nop nop nop bank a , col n ck ck# command address dq dqs,dqs# do n do n t0 t1 t2 t3 t4n t5n t4 t5 ck ck# command read nop nop nop nop nop address bank a, col n rl = 3 (al = 0, cl = 3) dq dqs, dqs# do n t0 t1 t2 t3 t3n t4n t4 t5 ck ck# command read nop nop nop nop nop address bank a, col n rl = 4 (al = 0, cl = 4) dq dqs, dqs# t0 t1 t2 t3 t3n t4n t4 t5 al = 1 cl = 3 rl = 4 (al + cl) don?t care transitioning data
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 32 ?2003 micron technology, inc. all rights reserved. dqs/dqs# is driven by the ddr2 sdram along with output data. the initial low state on dqs and high state on dqs# is known as the read preamble ( t rpre). the low state on dqs and high state on dqs# coincident with the last data-out element is known as the read postamble ( t rpst). upon completion of a burst, assuming no other commands have been initiated, the dqs will go high- z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), the valid data win- dow are depicted in figure 27 on page 39 and figure 28 on page 40. a detailed explanation of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) is shown in figure 29 on page 41. data from any read burst may be concatenated with data from a subsequent read command to pro- vide a continuous flow of data. the first data element from the new burst follows the last element of a com- pleted burst. the new read command should be issued x cycles after the first read command, where x equals bl / 2 cycles. this is shown in figure 19. figure 19: consecutive read bursts note: 1. 1. do n (or b ) = data-out from co lumn n (or column b ). 2. burst length = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. three subsequent elements of data-out ap pear in the programmed order following do b . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies only when read co mmands are issued to same device. ck ck# command read nop read nop nop nop nop address bank, col n bank, col b command read nop read nop nop nop address bank, col n bank, col b rl = 3 ck ck# command address dq dqs, dqs# rl = 4 dq dqs, dqs# do n do b do n do b t0 t1 t2 t3 t3n t4n t4 t5 t6 t5n t6n t0 t1 t2 t3 t2n nop t3n t4n t4 t5 t6 t5n t6n don?t care transitioning data t ccd t ccd
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 33 ?2003 micron technology, inc. all rights reserved. figure 20: nonconsecutive read bursts note: 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. three subsequent elements of data-out ap pear in the programmed order following do b . 5. shown with nominal t ac, t dqsck, and t dqsq. 6. example applies when read comma nds are issued to di fferent devices or nonconsecutive reads. nonconsecutive read data is illustrated in figure 20 on page 33. full-speed random read accesses within a page (or pages) can be performed. ddr2 sdram sup- ports the use of concurrent auto precharge timing, which is shown in table 7 on page 35. ddr2 sdram does not allow interrupting or trun- cating of any read burst using bl = 4 operations. once the bl = 4 read command is registered, it must be allowed to complete the entire read burst. how- ever, a read (with auto precharge disabled) using bl = 8 operation may be interrupted and truncated only by another read burst as long as the interrup- tion occurs on a four-bit boundary due to the 4 n prefetch architecture of ddr2 sdram. read burst bl = 8 operations may not be interrupted or truncated with any command except another read command as shown in figure 21 on page 34. ck ck# command read nop nop nop nop nop nop nop address bank, col n read bank, col b command address cl = 3 ck ck# command address dq dqs, dqs# cl = 4 dq dqs, dqs# do n t0 t1 t2 t3 t3n t4 t5 t7 t8 t6 t4n t6n t7n nop nop nop nop t5 t7 t8 t5n t6 t4n t7n read nop nop nop bank, col n read bank, col b t0 t1 t2 t3 t4 do b do n do b don?t care transitioning data
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 34 ?2003 micron technology, inc. all rights reserved. figure 21: read interrupted by read note: 1. burst length = 8 required, auto prec harge must be disabled (a10 = low). 2. read command can be issued to any valid bank and row addr ess (read command at t0 and t2 can be either same bank or different bank). 3. interupting read command mu st be issued exactly 2 x t ck from previous read. 4. auto precharge can be either enabled (a10 = high) or disabled (a10 = low) by the interupting read command. 5. nop or command inhibit comman ds are valid. precharge command cannot be issued to banks used for reads at t0 and t2. 6. example shown uses additive latency = 0; cas latency = 3, bl = 8, shown with nominal t ac, t dqsck, and t dqsq. d out d out d out ck ck# command dq dqs, dqs# cl = 3 (al = 0) read 1 t0 t1 t2 don?t care transitioning data nop 5 nop 5 d out t3 t4 t5 valid valid t6 valid read 3 d out d out d out d out d out d out d out d out valid valid valid t7 t8 t9 cl = 3 (al = 0) t ccd address a10 valid 4 valid 2 valid 2
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 35 ?2003 micron technology, inc. all rights reserved. data from any read burst must be completed before a subsequent write burst is allowed. an exam- ple of a read burst followed by a write burst is shown in figure 24. the t dqss (min) case is shown; the t dqss (max) case has a longer bus idle time. ( t dqss [min] and t dqss [max] are defined in the sec- tion on writes.) a read burst may be followed by a precharge command to the same bank provided that auto pre- charge is not activated. examples of read to pre- charge are shown in figure 22 for bl=4 and figure 23 for bl=8. the delay from read command to precharge command to the same bank is al + bl/2 + trtp - 2 clocks. if a10 is high when a read command is issued, the read with auto precharge function is engaged. the ddr2 sdram starts an auto pre- charge operation on the rising edge which is (al + bl/2) cycles later than the read with ap command if t ras (min) and t rtp are satisfied. if t ras (min) is not satisfied at the edge, the start point of auto pre- charge operation will be delayed until t ras (min) is satisfied. if t rtp (min) is not satisfied at the edge, the start point of the auto precharge operation will be delayed until t rtp (min) is satisfied. in case the inter- nal precharge is pushed out by t rtp, t rp starts at the point where the internal precharge happens (not at the next rising clock edge after this event). so for bl = 4 the minimum time from read with ap to the next activate command becomes al + ( t rtp + t rp)* (see figure 22 on page 35); for bl = 8 the time from read with ap to the next activate is al + 2 clocks + ( t rtp + t rp)* (see figure 23 on page 36), where * means each parameter term is divided by t ck and rounded up to the next inte- ger. in any event, internal precharge does not start ear- lier than two clocks after the last four-bit prefetch. figure 22: read to precharge bl = 4 table 7: read using concurrent auto precharge bl = burst length. from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units read with auto precharge read or read w/ap (bl/2) t ck write or write w/ap (bl/2) + 2 t ck precharge or active 1 t ck d out d out d out ck ck# command dq dqs, dqs# cl = 3 read read latency = 4 (al = 1, cl = 3), bl = 4, t rtp 2 clocks shown with nominal t ac, t dqsck, and t dqsq t0 t1 t2 don?t care transitioning data nop precharge d out t3 t4 t5 t6 active t7 address a10 al=1 nop bank a t rtp(min) bank a t ras(min) bank a t rp(min) nop nop al + bl/2 + t rtp - 2 clocks nop t rc(min) 4-bit prefetch valid valid
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 36 ?2003 micron technology, inc. all rights reserved. figure 23: read to precharge bl = 8 figure 24: read to write d out d out d out ck ck# command dq dqs, dqs# cl = 3 read read latency = 4 (al=1, cl=3), bl=8, t rtp 2 clocks shown with nominal t ac, t dqsck, and t dqsq t0 t1 t2 don?t care transitioning data nop d out t3 t4 t5 t6 t7 t8 address a10 al=1 nop bank a t rc(min) t rtp(min) nop nop d out d out d out d out first 4-bit prefetch second 4-bit prefetch t rp(min) precharge bank a bank a nop al + bl/2 + t rtp - 2 clocks nop active t ras(min) valid valid d out n + 3 d out n + 2 d out n + 1 ck ck# command dq dqs, dqs# al = 2 active n burst length = 4 shown with nominal t ac, t dqsck, and t dqsq t0 t1 t2 don?t care transitioning data read n nop nop d out n t3 t4 t5 nop write n t6 nop d in n + 3 d in n + 2 d in n + 1 wl = rl - 1 = 4 t7 t8 nop nop nop d in n t9 t10 t11 nop nop cl = 3 rl = 5 cas# read latency (cl) = 3 posted cas# additive latency (al) = 2 t rcd = 3
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 37 ?2003 micron technology, inc. all rights reserved. figure 25: bank read ? without auto precharge note: 1. do n = data-out from column n ; subsequent elements are ap plied in the programmed order. 2. burst length = 4 and al = 0 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t5. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. the precharge command can only be applied at t6 if t ras minimum is met. 8. read to precharge = al +bl/2 + t rtp-2 clocks. 9. i/0 pins, when entering or exiting high- z are not referenced to a specific voltag e level, but when the device begins to drive or no longer drives, respecively. ck ck# cke a10 ba0, ba1 t ck t ch t cl ra t rcd t ras 7 t rc t rp cl = 3 dm t0 t1 t2 t3 t4 t5 t7n t8n t6 t7 t8 dq 1 dqs, dqs# case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 1 dqs, dqs# t rpre t rpre t rpst t rpst t dqsck (min) t dqsck (max) t lz (min) t lz (max) t ac (min) t lz (min) do n t hz (max) t ac (max) t lz (min) do n nop 6 nop 6 command 5 act ra col n pre 7 bank x ra ra bank x bank x 4 9 9 99 act bank x nop 6 nop 6 nop 6 nop 6 t hz (min) one bank all banks don?t care transitioning data read 2 address 3 t rtp 8
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 38 ?2003 micron technology, inc. all rights reserved. figure 26: bank read ? with auto precharge note: 1. do n = data-out from column n; subsequent elements are applied in the programmed order. 2. burst length = 4, rl = 4 (al = 1, cl = 3) in the case shown. 3. enable auto precharge. 4. act = active, ra = row ad dress, ba = bank address. 5. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 6. the ddr2 sdram internally dela ys auto precha rge until both t ras (min) and t rtp (min) have been satisfied. 7. i/0 pins, when entering or exiting high- z are not referenced to a specific voltag e level, but when the device begins to drive or no longer drives, respecively. ck ck# cke a10 ba0, ba1 t ck t ch t cl ra t rcd t ras t rc t rp cl = 3 dm t0 t1 t2 t3 t4 t5 t7n t8n t6 t7 t8 dq 1 dqs,dqs# case 1: t ac (min) and t dqsck (min) case 2: t ac (max) and t dqsck (max) dq 1 dqs, dqs# t rpre t rpre t rpst t rpst t dqsck (min) t dqsck (max) t lz (min) t lz (max) t ac (min) t lz (min) do n t hz (max) t ac (max) t lz (max) do n nop 5 nop 5 command 5 act ra col n bank x ra ra bank x act bank x nop 5 nop 5 nop 5 nop 5 nop 5 t hz (min) don?t care transitioning data read 2,6 address al=1 4-bit prefetch t rtp internal precharge 3 7 7 77
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 39 ?2003 micron technology, inc. all rights reserved. figure 27: x4, x8 da ta output timing ? t dqsq, t qh, and data valid window note: 1. dqs transitioning af ter dqs transition define tdqsq window. dqs transitions at t2 and at t2n are ?early dqs,? at t3 are ?nominal dqs,? and at t3n are "late dqs." 2. for a x4, only two dqs apply. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transitions and ends with the last valid transition of dqs . 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transitions collectively when a bank is active. 6. the data valid window is derived for each dqs transition and is defined as t qh minus t dqsq. dq (last data valid) dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 dqs# dqs 1 dq (last data valid) dq (first data no longer valid) dq (first data no longer valid) all dqs and dqs, collectively 6 earliest signal transition latest signal transition t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 4 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 t hp 5 t hp 5 t hp 5 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 data valid window data valid window data valid window data valid window
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 40 ?2003 micron technology, inc. all rights reserved. figure 28: x16 data output timing ? t dqsq, t qh, and data valid window note: 1. dqs transitionin g after dqs transitions define the t dqsq window. ldqs defines the lower byte, and udqs defines the upper byte. 2. dq0, dq1, dq2, dq3, dq4, dq5, dq6, or dq7. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transitions and ends with the last valid transition of dqs. 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transitions collectively when a bank is active. 6. the data valid window is derive d for each dqs transition and is t qh minus t dqsq. 7. dq8, dq9, dq10, d11, dq12, dq13, dq14, or dq15. dq (last data valid) 2 dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 ldsq# ldqs 1 dq (last data valid) 2 dq (first data no longer valid) 2 dq (first data no longer valid) 2 dq0?dq7 and ldqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 data valid window data valid window dq (last data valid) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udqs# udqs 1 dq (last data valid) 7 dq (first data no longer valid) 7 dq (first data no longer valid) 7 dq8?dq15 and udqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 4 t qh 4 t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 data valid window data valid window data valid window data valid window data valid window upper byte lower byte data valid window
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 41 ?2003 micron technology, inc. all rights reserved. figure 29: data output timing ? t ac and t dqsck note: 1. t dqsck is the dqs output window relative to ck and is the?long -term? component of dqs skew. 2. dqs transitionin g after dqs transitions define t dqsq window. 3. all dqs must transition by t dqsq after dqs transitions, regardless of t ac. 4. t ac is the dq output window relative to ck and is the?long term? component of dq skew. 5. t lz (min) and t ac (min) are the first valid signal transitions. 6. t hz (max) and t ac (max) are the latest va lid signal transitions. 7. read command with cl=3, al=0 issued at t0. 8. i/0 pins, when entering or exiting high- z are not referenced to a specific voltag e level, but when the device begins to drive or no longer drives, respecively. ck ck# dqs#/dqs, or ldqs#/ldqs / udq#/udqs 2 t0 7 t1 t2 t3 t3n t4 t4n t5 t5n t6 t6n t7 t rpst t lz (min) t dqsck 1 (max) t dqsck 1 (min) t dqsck 1 (max) t dqsck 1 (min) t hz (max) t rpre dq (last data valid) dq (first data valid) all dqs collectively 3 t ac 4 (min) t ac 4 (max) t lz (min) t hz (max) t3 t3 t3n t4n t5n t6n t3n t3n t4n t4n t5n t5n t6n t6n t4 t5 t5 t6 t6 t3 t4 t5 t6 t4
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 42 ?2003 micron technology, inc. all rights reserved. writes write command the write command is used to initiate a burst write access to an active row. the value on the ba1- ba0 inputs selects the bank, and the address provided on inputs a0? i (where i = a9 for x8 and x16; or a9, a11 for x4) selects the starting column location. the value on input a10 determines whether or not auto pre- charge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. figure 30: write command input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm sig- nal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location (figure 40). write operation write bursts are initiated with a write command, as shown in figure 30. ddr2 sdram uses write latency (wl) equal to read latency minus 1 clock cycle (wl = rl - 1 = al + cl - 1). the starting column and bank addresses are provided with the write com- mand, and auto precharge is either enabled or dis- abled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the fi rst valid data-in element will be registered on the first rising edge of dqs follow- ing the write command, and subsequent data ele- ments will be registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write pream- ble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and the first corresponding rising edge of dqs ( t dqss) is spec- ified with a relatively wi de range (from 75 percent to 125 percent of one clock cycle). all of the write dia- grams show the nominal case, and where the two extreme cases (i.e., t dqss [min] and t dqss [max]) might not be intuitive, they have also been included. figure 31 shows the nominal case and the extremes of t dqss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored. data for any write burs t may be concatenated with a subsequent write command to provide con- tinuous flow of input data. the first data element from the new burst is applied after the last element of a completed burst. the new write command should be issued x cycles after the first write command, where x equals bl/2. figure 32 shows concatenated bursts of 4. an exam- ple of nonconsecutive writes is shown in figure 33. full-speed random write accesses within a page or pages can be performed as shown in figure 34. ddr2 sdram supports concurrent auto precharge options shown in table 8. ddr2 sdram does not allow interrupting or trun- cating any write burst using bl = 4 operation. once the bl = 4 write command is registered, it must be allowed to complete the entire write burst cycle. however, a write (with auto precharge disabled) using bl = 8 operations may be interrupted and trun- cs# we# cas# ras# cke ca a10 bank address high en ap dis ap ba ck ck# ca = column address ba = bank address en ap = enable auto precharge dis ap = disable auto precharge don?t care address
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 43 ?2003 micron technology, inc. all rights reserved. cated only by another write burst as long as the interruption occurs on a four-bit boundary due to the 4 n prefetch architecture of ddr2 sdram. write burst bl = 8 operations may not be interrupted or truncated with any command except another write command as shown in figure 35. data for any write burst may be followed by a sub- sequent read command. to follow a write t wtr should be met as shown in figure 36. t wtr is defined as min(2 or t wtr/ t ck rounded up to the next integer). data for any write burst may be followed by a subse- quent precharge command. t wr must be met as shown in figure 30. t wr starts at the end of the data burst regardless of the data mask condition. table 8: write using concurrent auto precharge cl = cas latency, bl = burst length from command (bank n ) to command (bank m ) minimum delay (with concurrent auto precharge) units write with auto precharge read or read w/ap (cl-1) + (bl/2) + t wtr t ck write or write w/ap (bl/2) t ck precharge or active 1 t ck
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 44 ?2003 micron technology, inc. all rights reserved. figure 31: write burst note: 1. di b = data-in for column b . 2. three subsequent elements of data-in are ap plied in the programmed order following di b . 3. a burst of 4 is shown with al = 0, cl = 3; thus, wl = 2. 4. a10 is low with the write command (auto precharge is disabled). 5. subsequent rising dqs signals must align to the clock within 0.25 t ck dqs, dqs# t dqss (max) t dqss (nom) t dqss (min) t dqss dm dq ck ck# command write nop nop address bank a , col b nop nop t0 t1 t2 t3 t2n t4 t3n dqs, dqs# t dqss 5 5 5 dm dq dqs, dqs# t dqss dm dq di b di b di b don?t care transitioning data
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 45 ?2003 micron technology, inc. all rights reserved. figure 32: consecutive write to write note: 1. di b , etc. = data-i n for column b , etc. 2. three subsequent elements of data-in are ap plied in the programmed order following di b . 3. three subsequent elements of data-in are ap plied in the programmed order following di n . 4. a burst of 4 is shown with al = 0, cl = 3; thus, wl = 2. 5. each write command may be to any bank. 6. subsequent rising dqs signals must align to the clock within 0.25 t ck figure 33: nonconsecutive write to write note: 1. di b , etc. = data-i n for column b , etc. 2. three subsequent elements of data-in are ap plied in the programmed order following di b . 3. three subsequent elements of data-in are ap plied in the programmed order following di n . 4. a burst of 4 is shown. al = 0, cl = 3; thus, wl = 2. 5. each write command may be to any bank. 6. subsequent rising dqs signals must align to the clock within 0.25 t ck ck ck# command write nop write nop nop nop address bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t6 t5n t3n t1n dq dqs, dqs# dm di n di b don?t care transitioning data t dqss t dqss (nom) wl = 2 t ccd wl = 2 6 ck ck# command write nop nop nop nop nop address bank, col b write bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t3n t5n t6 t6n dq dqs, dqs# dm di n di b t dqss (nom) t dqss don?t care transitioning data wl = 2 wl = 2 6
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 46 ?2003 micron technology, inc. all rights reserved. figure 34: rand om write cycles note: 1. di b , etc. = data-i n for column b , etc. 2. three subsequent elements of data-in are ap plied in the programmed order following di b . 3. three subsequent elements of data-in are ap plied in the programmed order following di n . 4. an burst of 4 is shown. al = 0, cl = 3; thus, wl = 2. 5. each write command may be to any bank. 6. subsequent rising dqs signals must align to the clock within 0.25 t ck figure 35: write in terrupted by write note: 1. burst length = 8 required, auto prec harge must be disabled (a10 = low). 2. write command can be issued to any valid bank and ro w address (write command at t0 and t2 can be either same bank or different bank). 3. interupting write command must be issued exactly 2 x t ck from previous write. 4. auto precharge can be either enabled (a10 = high) or disabled (a10 = low) by th e interupting write command. 5. nop or command inhibit commands are va lid. precharge command can not be i ssued to banks used for writes at t0 and t2. 6. earliest write-to-prec harge timing for write at t0 is wl + bl/2 + t wr where t wr starts with t7 and not t5 (since bl = 8 from mr and not the truncated length). 7. example shown uses additive late ncy = 0; cas latency = 4, bl = 8. 8. subsequent rising dqs signals must align to the clock within 0.25 t ck ck ck# command write nop write nop nop nop address bank, col b nop bank, col n t0 t1 t2 t3 t2n t4 t5 t4n t6 t5n t3n t1n dq dqs, dqs# dm di n di b don?t care transitioning data t dqss t dqss (nom) wl = 2 t ccd wl = 2 6 d in a + 3 d in a + 2 d in a + 1 ck ck# command dq dqs, dqs# wl = 3 write 1 a t0 t1 t2 don?t care transitioning data d in a t3 t4 t5 t6 write 3 b d in b + 3 d in b + 2 d in b + 1 d in b d in b + 7 d in b + 6 d in b + 5 d in b + 4 t7 t8 t9 wl = 3 2 clock requirement address a10 valid 4 valid 2 valid 2 valid 6 valid 6 valid 6 nop 5 nop 5 nop 5 nop 5 nop 5 8
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 47 ?2003 micron technology, inc. all rights reserved. figure 36: write to read note: 1. di b = data-in for column b ; dout n = data out from column n. 2. a burst of 4 is shown; al = 0, cl = 3; thus, wl = 2. 3. one subsequent element of data-in is ap plied in the programmed order following di b . 4. t wtr is referenced from the first positive ck edge after the last data-in pair. 5. a10 is low with the write command (auto precharge is disabled). 6. t wtr is defined as min(2 or t wtr/ t ck rounded up to the next integer). 7. required for any re ad following a write to the same device. 8. subsequent rising dqs signals must align to the clock within 0.25 t ck t dqss (nom) ck ck# command write nop nop nop nop nop nop nop address bank a , col b bank a , col n read t0 t1 t2 t3 t2n t4 t5 t9n t3n t6 t7 t8 t9 t wtr 7 cl = 3 cl = 3 cl = 3 dq dqs, dqs# dm di b t dqss (min) dq dqs, dqs# dm di b t dqss (max) dq dqs, dqs# dm di b do ut do ut don?t care transitioning data t dqss t dqss t dqss nop do ut 8 8 8
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 48 ?2003 micron technology, inc. all rights reserved. figure 37: write to precharge note: 1. di b = data-in for column b . 2. three subsequent elements of data-in are ap plied in the programmed order following di b . 3. bl=4; cl = 3; al = 0; thus, wl = 2. 4. t wr is referenced from the first positive ck edge after the last data-in pair. 5. the precharge and write commands are to the same ba nk. however, the precharge and write commands may be to different banks, in which case t wr is not required and the precharge command could be applied earlier. 6. a10 is low with the write command (auto precharge is disabled). 7. pre = precharge command. 8. subsequent rising dqs signals must align to the clock within 0.25 t ck t dqss (nom) ck ck# command write nop nop nop nop nop address bank a , col b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t3n t6 t7 t wr t rp dq dqs# dqs dm di b t dqss (min) dq dqs# dqs dm di b t dqss (max) dq dqs# dqs dm di b don?t care transitioning data t dqss t dqss t dqss pre 7 8 8 8
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 49 ?2003 micron technology, inc. all rights reserved. figure 38: bank write? without auto precharge note: 1. di n = data-in from column n; subsequent el ements are applied in the programmed order. 2. bl = 4, al = 0, and wl = 2 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t9. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. 8. t dss is applicable during t dqss (max) and is referenced from ck t6 or t7. 9. subsequent rising dqs signals must align to the clock within 0.25 t ck ck ck# cke a10 ba0, ba1 t ck t ch t cl ra t rcd t ras t rp t wr t0 t1 t2 t3 t5 t6 t6n t7 t8 t9 t5n nop 6 nop 6 command 5 3 9 act ra col n write 2 nop 6 one bank all banks bank x pre bank x nop 6 nop 6 nop 6 t dqsl t dqsh t wpst bank x 4 dq 1 dm di n don?t care transitioning data t dqss (nom) t wpre dqs, dqs# address nop 6 wl=2 t4
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 50 ?2003 micron technology, inc. all rights reserved. figure 39: bank write ?with auto precharge note: 1. di n = data-in from column n; subsequent el ements are applied in the programmed order. 2. burst length = 4, al = 0, and wl = 2 shown. 3. enable auto precharge. 4. act = active, ra = row ad dress, ba = bank address. 5. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 6. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. 7. t dss is applicable during t dqss (max) and is referenced from ck t6 or t7. 8. wr is programmed via mr[11,10,9] and is calculated by dividing t wr(ns) by t ck and rounding up to the next integer value. 9. subsequent rising dqs signals must align to the clock within 0.25 t ck ck ck# cke a10 ba0, ba1 t ck t ch t cl ra t rcd t ras t rp wr 8 t0 t1 t2 t3 t4 t5 t5n t6 t7 t8 t6n nop 5 nop 5 command 4 3 act ra col n write 2 nop 5 bank x nop 5 bank x nop 5 nop 5 nop 5 t dqsl t dqsh t wpst dq 1 dm t dqss (nom) don?t care transitioning data t wpre dqs,dqs# address t9 nop 5 wl = 2 di n 9
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 51 ?2003 micron technology, inc. all rights reserved. figure 40: write?dm operation note: 1. di n = data-in from column n ; subsequent elements are ap plied in the programmed order. 2. burst length = 4, al = 1, and wl = 2 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a10 is high at t11. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t6 or t7. 8. t dss is applicable during t dqss (max) and is referenced from ck t7 or t8. 9. t wr starts at the end of the data burst regardless of the data mask condition. 10. subsequent rising dqs signals must align to the clock within 0.25 t ck ck ck# cke a10 ba0, ba1 t ck t ch t cl ra t rcd t ras t rp a t wr 9 t0 t1 t2 t3 t4 t5 t7n t6 t7 t8 t6n nop 6 nop 6 command 5 3 act ra col n write 2 nop 6 one bank all banks bank x bank x nop 6 nop 6 nop 6 nop 6 nop 6 nop 6 t dqsl t dqsh t wpst bank x 4 dq 1 dm don?t care transitioning data t dqss (nom) t wpre pre dqs, dqs# address t9 t10 t11 al=1 wl=2 di n 10
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 52 ?2003 micron technology, inc. all rights reserved. figure 41: data input timing note: 1. t dsh (min) generally occurs during t dqss (min). 2. t dss (min) generally occurs during t dqss (max). 3. write command issued at t0. 4. for x16, ldqs controls the lower by te and udqs controls the upper byte. 5. write command wi th wl=2 (cl=3, al=0) issued at t0. 6. subsequent rising dqs signals must align to the clock within 0.25 t ck dqs# dqs t dqss(nominal) t dqsh t wpst t dqsl t dss 2 t dsh 1 t dsh 1 t dss 2 dm dq ck ck# t1 t0 t1n t2 t2n t3 t4 t3n di don?t care transitioning data t wpre 6
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 53 ?2003 micron technology, inc. all rights reserved. precharge precharge command the precharge command, illustrated in figure 42, is used to deactivate the open row in a par- ticular bank or the open row in all banks. the bank(s) will be available for a subsequent row activation a specified time ( t rp) after the precharge command is issued, except in the case of concurrent auto pre- charge, where a read or write command to a differ- ent bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. precharge operation input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba1-ba0 select the bank. otherwise ba1-ba0 are treated as ?don?t care.? when all banks are to be precharged, inputs ba1- ba0 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. t rpa timing applies when the pre- charge(all) command is issued, regardless of the number of banks already open or closed. if a single- bank precharge command is issued, t rp timing applies. figure 42: precharge command cs# we# cas# ras# cke a10 ba0, ba1 high all banks one bank ba address ck ck# ba = bank address (if a10 is low; otherwise ?don?t care?) don?t care
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 54 ?2003 micron technology, inc. all rights reserved. self refresh self refresh command the self refresh command can be used to retain data in the ddr2 sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 sdram retains data without external clocking. all power supply inputs (including v ref ) must be maintained at valid levels upon entry/exit and during self refresh operation. the self refresh command is initiated like a refresh command except cke is (low). the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). clock should remain stable and meet- ing t cke specifications at least 1 x t ck after entering self refresh mode. all command and address input sig- nals except cke are ?don?t care? during self refresh. the procedure for exiting self refresh requires a sequence of commands. first, ck, ck# must be stable and meeting t ck specifications at least 1 x t ck prior to cke going back high. once cke is high ( t cke(min) has been satified with four clock registrations), the ddr2 sdram must have nop or deselect com- mands issued for t xsnr because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply nop or deselect com- mands for 200 clock cycles before applying any other command.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 55 ?2003 micron technology, inc. all rights reserved. figure 43: self refresh note: 1. clock must be stable and meeting t ck specifications at least 1 x t ck after entering self refresh and at least 1 x t ck prior to exiting self refresh mode. 2. device must be in the all banks idle sta te prior to entering self refresh mode. 3. t xsnr is required before any non-read command can be applied. 4. t xsrd (200 cycles of ck) is required before a read command can be applied at state td0. 5. ref = refr esh command. 6. self refresh exit is asynchronous, however, t xsnr and t xsrd timing starts at the first rising clock edge where cke high satisfies t isxr. 7. nop or deselect commands are required prior to exiting self re fresh until state tc0, wh ich allows any non-read command. 8. odt must be disabled and r tt off ( t aofd and t aofpd have been satisfied) prior to entering self refresh at state t1. 9. once self refresh has been entered t cke(min) must be satisfied prior to exiting self refresh. 10. cke must stay high; t cke(min) high = 3 clock registrations. ck 1 ck# command 5 nop ref address cke 1 valid dq dm dqs#, dqs nop 7 t rp 2 t ch t cl t ck 1 t ck 1 t xsnr 3,6 t isxr 6 enter self refresh mode (synchronous) exit self refresh mode (asynchronous) t0 t1 ta2 ta1 don?t care ta0 tc0 tb0 t xsrd 4,6 valid 3 t cke (min) 10 nop 7 t cke (min) 9 t2 odt 8 t aofd / t aofpd 8 8 td0 valid 4 8 valid 3 indicates a break in time scale
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 56 ?2003 micron technology, inc. all rights reserved. refresh refresh command refresh is used during normal operation of the ddr2 sdram and is analogous to cas#-before- ras# (cbr) refresh. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an refresh command. the 256mb ddr2 sdram requires refresh cycles at an average inter- val of 7.8125s (maximum). to allow for improved effi- ciency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is pro- vided. a maximum of eight refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interval between any refresh command and the next refresh command is 9 7.8125s (70.3s). the refresh period begins when the refresh command is registered and ends t rfc (min) later. figure 44: refresh mode note: 1. pre = precharge, act = active, ar = refresh, ra = ro w address, ba = bank address. 2. nop commands are shown for ease of i llustration; other valid co mmands may be possible at these times. cke must be active during clock positive transitions. 3. ?don?t care? if a10 is high at this po int; a10 must be high if more than one bank is active (i.e., must precharge all active banks). 4. dm, dq, and dqs signals are all ?don?t care?/high-z for operations shown. 5. the second refresh is not required and is only shown as an example of two back-to-back refresh commands. ck ck# command 1 nop 2 nop 2 nop 2 pre cke ra address a10 1 bank 1 bank(s) 3 ba ref nop 2 ref 5 nop 2 act nop 2 one bank all banks t ck t ch t cl ra dq 4 dqs, dqs# 4 t0 t1 t2 t3 t4 ta0 tb0 ta1 tb1 tb2
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 57 ?2003 micron technology, inc. all rights reserved. power-down mode ddr2 sdrams support multiple power-down modes that allow a signific ant power savings over nor- mal operating modes. the cke input pin is used to enter and exit different power-down modes. power- down entry and exit timings are shown in figure 45. detailed power-down entry conditions are shown in figure 46 through figure 53. the truth table for cke is shown in table 9 on page 59 for ddr2 sdram. ddr2 sdrams require cke to be registered high (active) at all times that an access is in progress: from the issuing of a read or write command until com- pletion of the burst. thus a clock suspend is not sup- ported. for reads, a burst completion is defined when the read postamble is sati sfied; for writes, a burst completion is defined when the write postamble and t wr or t wtr are satisfied, and shown in figure 48 and figure 49. t wtr is defined as min(2 or t wtr/ t ck rounded up to the next integer). power-down in figure 45, is entered when cke is registered low coincident with a nop or deselect command. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down. if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and out- put buffers, excluding ck, ck#, odt, and cke. for maximum power savings, the dll is frozen during pre- charge power-down. exiting active power-down requires the device to be at the same voltage and fre- quency as when it entered power-down. exiting pre- charge power-down requires the device to be at the same voltage as when it entered power-down; how- ever, the clock frequency is allowed to change (see "precharge power-down clock frequency change" on page 7.) the maximum duration for either active or pre- charge power-down is limited by the refresh require- ments of the device t rfc (max). the minimum duration for power-down entry and exit is limited by t cke(min) parameter. while in power-down mode, cke low, a stable clock sign al, and stable power sup- ply signals must be maintained at the inputs of the ddr2 sdram, while all other input signals are ?don?t care? except odt. detailed odt timing diagrams for different power-down modes are shown for figure 3 on page 10 through figure 8 on page 15. the power-down state is synchronously exited when cke is registered hi gh (in conjunction with a nop or deselect command) as shown in figure 45.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 58 ?2003 micron technology, inc. all rights reserved. figure 45: power-down note: 1. if this command is a precharge (or if the device is alread y in the idle state), then the power-down mode shown is pre- charge power-down. if this command is an active (or if at least one row is alr eady active), then the power-down mode shown is active power-down. 2. no column accesses are allowed to be in progress at the time power-down is entered. 3. t cke (min) of 3 clocks means cke must be registered on thre e consecutive positve clock ed ges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not trainsition from its valid le vel during the time period of t is + 2 * t ck + t ih. cke must not transition during its t is and t ih window. 4. t xp timing is used for exit precharge power-down and active power-down to any non-read command. 5. t xprd timing is used for exit prec harge power-down to any read command 6. t xard timing is used for exit active power-down to read command if 'fast ex it' is selected via mr (bit 12 = 0). 7. t xards timing is used for exit active power-down to read command if 'slow exit' is selected via mr (bit 12 = 1). ck ck# command nop nop nop address cke dq dm dqs, dqs# valid t ck t ch t cl enter power-down mode 2 exit power-down mode don?t care t cke (min) 3 t cke (min) 3 valid valid 1 valid t xp 4 , t xprd 5 t xard 6, t xards 7 valid valid t1 t2 t3 t4 t5 t6 t7 t8 t is t ih t ih
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 59 ?2003 micron technology, inc. all rights reserved. note: 1. cke ( n ) is the logic state of cke at clock edge n ; cke ( n -1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr2 sdram immediately prior to clock edge n . 3. command ( n ) is the command registered at clock edge n , and action ( n ) is a result of command (n). 4. all states and sequences not shown are il legal or reserved unless explicitely described elsewhere in this document. 5. on self refresh exit, deselect or nop commands must be issued on every clock edge occurring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 6. self refresh mode can only be ente red from the all banks idle state. 7. must be a legal command as defined in the command truth table. 8. valid commands for power-down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselect only. 10. power-down and self refresh can not be entered while read or write operations, lo ad mode operations, or pre- charge or refresh operations are in progress. see power-down and self refresh sections for a list of detailed restric- tions. 11. minimum cke high time is t cke = 3 x t ck. minimum cke low time is t cke = 3 x t ck. this requires a minimum of 3 clock cycles of registration. 12. the state of on-die termination (odt) doe s not affect the states described in this table. the odt func tion is not avail- able during self refresh. see odt section for more deta ils and specific restrictions. 13. power-down modes do not perform any refresh operations. th e duration of power-down mode is therefore limited by the refresh requirements. 14. ?x? means ?don?t care? (inc luding floating around v ref ) in self refresh and power-down. however, odt must be driven high or low in power-down if the odt function is enabled via emr(1). table 9: cke truth table notes 1?3, 12 current state cke command ( n ) cs#,ras#,cas#,we# action ( n ) notes previous cycle ( n -1) current cycle ( n ) power down l l x maintain power-down 13, 14 l h deselect or nop power-down exit 4, 8 self refresh l l x maintain self refresh 14 l h deselect or nop self refresh exit 4, 5, 9 bank(s) active h l deselect or nop active power-down entry 4, 8, 10, 11 all banks idle h l deselect or nop pre charge power-down entry 4, 8, 10 h l refresh self refresh entry 6, 9, 11 h h refer to command truth table 1 on page 7 7
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 60 ?2003 micron technology, inc. all rights reserved. figure 46: read to power-down entry note: 1. power-down entry may occur after the read burst completes. 2. in the example shown, read bu rst completes at t5; earliest power-down entry is at t6. figure 47: read with auto precharge to power-down entry note: 1. power-down entry may occur 1 x t ck after the internal precharge is issued and may be prior to t rp being satisfied. 2. timing shown above assumes internal precharge was issued at t5 or earlier. 3. refer to read-to-precharge section fo r internal precharge timing details. d out d out d out ck ck# command dq dqs, dqs# rl = 3 t0 t1 t2 don?t care transitioning data nop nop d out t3 t4 t5 valid t6 t7 t8 t9 t cke (min) address a10 nop cke read valid t10 power-down 1 entry nop d out d out d out ck ck# command dq dqs, dqs# rl = 3 t0 t1 t2 don?t care transitioning data nop nop d out t3 t4 t5 valid valid t6 t7 t8 t9 t cke (min) address a10 nop cke read valid t10 power-down 1 entry nop
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 61 ?2003 micron technology, inc. all rights reserved. figure 48: write to power-down entry figure 49: write with auto pr echarge to power-down entry note: 1. write recovery (wr) is programmed through mr[9,10,11 ] and represents [ t wr (min) ns / t ck] rounded up to next inte- ger t ck. 2. internal precharge occurs at ta0 when wr ha s completed; power-down entry may occur 1 x t ck later at ta1 prior to t rp being satisfied. figure 50: refresh comma nd to power-down entry note: 1. the earliest precharge powe r-down entry may occur is at t2 which is 1 x t ck after the refresh command. precharge power down entry occurs prior to t rfc (min) being satisfied. d out d out d out ck ck# command dq dqs, dqs# wl = 3 t0 t1 t2 don?t care transitioning data nop nop d out t3 t4 t5 valid valid t6 valid 1 t7 t8 t9 t cke (min) address a10 nop cke write valid t10 power-down entry twtr nop d out d out d out ck ck# command dq dqs, dqs# wl = 3 t0 t1 t2 don?t care transitioning data nop nop d out t3 t4 t5 valid valid ta0 valid 2 nop ta1 ta2 ta3 t cke (min) address a10 nop cke write valid ta4 power-down entry wr 1 indicates a break in time scale ck ck# command don?t care t0 t1 valid refresh t2 t3 t4 t5 t cke (min) cke t6 power-down 1 entry 1 x t ck nop
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 62 ?2003 micron technology, inc. all rights reserved. figure 51: active comma nd to power-down entry note: 1. the earliest precharge powe r-down entry may occur is at t2, which is 1 x t ck after the active command. active power-down entry occurs prior to t rcd (min) being satisfied. figure 52: precharge comma nd to power-down entry note: 1. the earliest power-down entry may occur is at t2, which is 1 x t ck after the precharge co mmand. power-down entry occurs prior to t rp (min) being satisfied. ck ck# command don?t care t0 t1 valid active t2 nop t3 t4 t5 t cke (min) cke t6 power-down 1 entry 1 t ck address valid ck ck# command don?t care t0 t1 valid precharge t2 nop t3 t4 t5 t cke (min) cke t6 power-down 1 entry 1 x t ck address a10 valid all banks vs single bank
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 63 ?2003 micron technology, inc. all rights reserved. figure 53: load mode co mmand to power-down entry note: 1. the earliest precharge po wer-down entry is at t3, which is after t mrd is satisfied. 2. all banks must be in the precharged state and t rp met prior to issuing lm command. 3. valid address for lm command includes mr, emr, emr(2), and emr(3) registers. ck ck# command don?t care t0 t1 valid lm t2 nop t3 t4 t5 t cke (min) cke t6 power-down 1 entry t mrd address valid 3 t rp 2 t7 nop
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 64 ?2003 micron technology, inc. all rights reserved. precharge power-down clock frequency change when the dram is in precharged power-down mode, on-die termination (odt) must be turned off and cke must be at a logic low level. a minimum of two clocks must pass after cke goes low before clock frequency may change. the dram input clock fre- quency is allowed to change only within minimum and maximum operating frequencies specified for the par- ticular speed grade. during input clock frequency change, odt and cke must be held at stable low lev- els. once the input clock frequency is changed, new stable clocks must be provided to the dram before precharge power-down may be exited and dll must be reset via emr after precharge power-down exit. depending on the new clock frequency an additional mr command may need to be issued to appropriately set the wr mr[11, 10, 9] register. during the dll relock period of 200 cycles, odt must remain off. after the dll lock time, the dram is ready to operate with a new clock frequency. figure 54: input clock frequency change during pr echarge power down mode note: 1. if this command is a precharge (or if the device is alread y in the idle state), then the power-down mode shown is pre- charge power-down, which is required prior to th e clock frequency change. 2. a minimum of 2 x t ck is required after entering precharge power-down prior to changing clock frequencies. 3. once the new clock frequency has chan ged and is stable, a minimum of 1 x t ck is required prior to exiting precharge power-down. 4. minimum cke high time is t cke = 3 x t ck. minimum cke low time is t cke = 3 x t ck. this requires a minimum of 3 clock cycles of registration. ck ck# command valid 1 nop addr cke dq dm dqs, dqs# nop t ck enter precharge power-down mode exit precharge power-down mode t0 t1 t3 ta0 t2 don?t care valid t cke (min) 4 t cke (min) 4 t xp lm dll reset valid valid nop t ch t cl ta1 ta2 tb0 ta3 2 x t ck (min) 2 1 x t ck (min) 3 t ch t cl t ck odt 200 x t ck nop ta4 previous clock frequency new clock frequency frequency change high-z high-z indicates a break in time scale
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 65 ?2003 micron technology, inc. all rights reserved. reset function (cke low anytime) ddr2 sdram applications may go into a reset state at any time during norm al operation. if an appli- cation enters a reset condition, the cke input pin is used to ensure the ddr2 sdram device resumes nor- mal operation after reinitializing. all data will be lost during a reset condition; however, the ddr2 sdram device will continue to operate properly if the follow- ing conditions outlined in this section are satisfied. the reset condition defined here assumes all sup- ply voltages (v dd , v dd q, v dd l, and v ref ) are stable and meet all dc specifications prior to, during, and after the reset operation. all other input pins of the ddr2 sdram device are a ?don?t care? during reset with the exception of cke. if cke asynchronously drops low during any valid operation (including a re ad or write burst), the memory controller must satisfy the timing parameter t d elay before turning off the cl ocks. stable clocks must exist at the ck, ck# inputs of dram before cke is raised high, at which time the normal initialization sequence must occur (see ?initialization? on page 9). the ddr2 sdram is now ready for normal operation after the initialization sequence. figure 55 shows the proper sequence for a reset condition. figure 55: reset condition note: 1. in certain cases where a read cycle is interupted, cke going high may result in th e completion of the burst. cke rtt ba0, ba1 high-z dm 7 dqs 7 high-z address a10 ck ck# t cl command 6 nop pre all banks ta0 don?t care transitioning data t rp a t cl t ck odt dq 7 high-z t = 400ns (min) tb0 read nop t0 t1 t2 col n bank a t delay d out d out ( ) ( ) read nop col n bank b d out high-z high-z unknown r tt on system reset t3 t4 t5 start of normal initialization sequence nop indicates a break in time scale t cke (min) 1 for initiliza- tion timing, see time sequence ta0 in figure 4, ddr2 power-up and initialization, on page 10
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 66 ?2003 micron technology, inc. all rights reserved. odt timing there are two timing categories for odt, turn-on and turn-off. during active mode (cke high) and ?fast-exit? power-down mode (any row of any bank open, cke low, mr[bit12 = 0]), t aond, t aon, t aofd, and t aof timing parameters are applied as shown in figure 56 and table 10 on page 67. during ?slow-exit? power-down mode (any row of any bank open, cke low, mr[bit12=1]) and precharge power-down mode (all banks/rows precharged and idle, cke low), t aonpd and t aofpd timing parameters are applied as shown in figure 57 and table 11 on page 68. odt turn-off timing prior to entering any power- down mode is determined by the parameter t anpd (min) shown in figure 58. at state t2 the odt high signal satisfies t anpd (min) prior to entering power- down mode at t5. when t anpd (min) is satisfied t aofd and t aof timing parameters apply. figure 58 also shows the example where t anpd (min) is not satisfied since odt high does not occur until state t3. when t anpd (min) is not satisfied, t aofpd tim- ing parameters apply. odt turn-on timing prior to entering any power- down mode is determined by the parameter t anpd shown in figure 59. at state t2, the odt high signal satisfies t anpd (min) prior to entering power-down mode at t5. when t anpd (min) is satisfied t aond and t aon timing parameters apply. figure 59 also shows the example where t anpd (min) is not satis- fied since odt high does not occur until state t3. when t anpd (min) is not satisfied, t aonpd timing parameters apply. odt turn-off timing after exiting any power-down mode is determined by the parameter t axpd (min) shown in figure 60. at state ta1, the odt low signal satisfies t axpd (min) after exiting power-down mode at state t1. when t axpd (min) is satisfied, t aofd and t aof timing parameters apply. figure 60 also shows the example where t axpd (min) is not satisfied since odt low occurs at state ta0. when t axpd (min) is not satisfied, t aofpd timing parameters apply. odt turn-on timing after exiting any power-down mode is determined by the parameter t axpd (min) shown in figure 61. at state ta1, the odt high signal satisfies t axpd (min) after exiting power-down mode at state t1. when t axpd (min) is satisfied, t aond and t aon timing parameters apply. figure61 also shows the example where t axpd (min) is not satisfied since odt high occurs at state ta0. when t axpd (min) is not satisfied, t aonpd timing parameters apply.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 67 ?2003 micron technology, inc. all rights reserved. figure 56: odt timing for active or ?fast-exit? powe r-down mode t1 t0 t2 t3 t4 t5 t6 valid valid valid valid valid valid valid ck# ck cke t aof (max) odt rtt t aon (min) t aon (max) t aond addr t aofd t aof (min) valid valid valid valid valid valid valid cmd t ch t cl t ck don?t care r tt unknown r tt on table 10: odt timing for active and ?fast-exit? power-down modes parameter symbol min max units odt turn-on delay t aond 22 t ck odt turn-on t aon t ac (min) t ac (max) + 1,000 ps odt turn-off delay t aofd 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 ps
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 68 ?2003 micron technology, inc. all rights reserved. figure 57: odt timing for ?slow-exit? or precharge power-down modes don?t care t1 t0 t2 t3 t4 t5 t6 valid valid valid valid valid valid valid ck# ck cke odt r tt addr valid valid valid valid valid valid valid cmd t ch t cl t ck t aonpd (min) t aonpd (max) t aofpd (min) t aofpd (max) transitioning r tt t7 valid valid r tt unknown r tt on table 11: odt timing for ?slow-exit? and precha rge power-down modes parameter symbol min max units odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck+ t ac (max) + 1,000 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 69 ?2003 micron technology, inc. all rights reserved. figure 58: odt ?turn off? timing s when entering power-down mode t1 t0 t2 t3 t4 t5 t6 nop nop nop nop nop nop nop ck# ck cke t anpd (min) odt r tt t aof (min) t aof (max) t aofd odt r tt t aofpd (min) t aofpd (max) don?t care transitioning r tt r tt unknown rtt on table 12: odt ?turn off? timing s when entering power-down mode parameter symbol min max units odt turn-off delay t aofd 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 3 t ck
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 70 ?2003 micron technology, inc. all rights reserved. figure 59: odt ?turn-on? timing when entering power-down mode t1 t0 t2 t3 t4 t5 t6 nop nop nop nop nop nop nop ck# ck cke t anpd (min) odt r tt t aon (min) t aon (max) t aond odt r tt t aonpd (min) t aonpd (max) don?t care transitioning r tt r tt unknown r tt on table 13: odt ?turn-on? timing when entering power-down mode parameter symbol min max units odt turn-on delay t aond 22 t ck odt turn-on t aon t ac (min) t ac (max) + 1,000 ps odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 3 t ck
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 71 ?2003 micron technology, inc. all rights reserved. figure 60: odt ?turn-off? timing when exiting power-down mode t1 t0 t2 t3 t4 ta0 ta1 nop nop nop nop nop nop nop ck# ck cke t axpd (min) odt r tt t aof (max) odt r tt t aofpd (min) t aofpd (max) command t cke (min) ta2 ta3 ta4 ta5 nop nop nop nop don?t care transitioning r tt r tt unknown r tt on t aof (min) t aofd indicates a break in time scale table 14: odt ?turn-of? timing when exiting power-down mode parameter symbol min max units odt turn-off delay t aofd 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down exit latency t axpd 8 t ck
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 72 ?2003 micron technology, inc. all rights reserved. figure 61: odt ?turn on? timing when exiting power-down mode t1 t0 t2 t3 t4 ta0 ta1 nop nop nop nop nop nop nop ck# ck cke t axpd (min) command ta2 ta3 ta4 ta5 nop nop nop nop odt r tt t aon (min) t aon (max) t aond odt r tt t aonpd (min) t aonpd (max) don?t care transitioning r tt r tt unknown r tt on indicates a break in time scale t cke (min) table 15: odt ?turn on? timing when exiting power-down mode parameter symbol min max units odt turn-on delay t aond 22 t ck odt turn-on t aon t ac (min) t ac (max) + 1,000 ps odt turn-on (power-down mode) t aonpd t ac (min) + 2,000 2 x t ck + t ac (max) + 1,000 ps odt to power-down exit latency t axpd 8 t ck
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 73 ?2003 micron technology, inc. all rights reserved.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 74 ?2003 micron technology, inc. all rights reserved. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. th is is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. figure 62: example temper ature test point location table 16: absolute maximum dc ratings symbol parameter min max units v dd v dd supply voltage relative to v ss -1.0 2.3 v v dd q v dd q supply voltage relative to v ss q -0.5 2.3 v v dd l v dd l supply voltage relative to vssl -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature (t case ) 1 -55 100 c t c operating temperature (t case ) 1,2 085c i i input leakage current any input 0v <= v in <= vdd (all other pins not under test = 0v) -5 5 ua i oz output leakage current 0v <= v out <= v dd q dqs and odt are disabled -5 5 ua i v ref v ref leakage current v ref = valid v ref level -2 2 ua note: 1. max operating case temperature; t c is measured in the center of the package illustrated in figure 62. 2. device functionality is no t guaranteed if the dram de vice exceeds the maximum t c during operation. 8.00 4.00 12.00 6.00 test point 8mm x 12mm ?fp? fbga 8.00 4.00 14.00 7.00 8mm x 14mm ?fg? fbga
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 75 ?2003 micron technology, inc. all rights reserved. ac and dc operating conditions note: 1. v dd and v dd q must track each other. v dd q must be less than or equal to v dd . 2. v ref is expected to equal v dd q/2 of the transmitting device and to track vari ations in the dc level of the same. peak-to- peak noise (non-common mode) on v ref may not exceed 1% of the dc value. peak-to-peak ac noise on v ref may not exceed 2 percent of v ref ( dc ). this measurement is to be taken at the nearest v ref bypass capacitor. 3. v tt is not applied directly to the device. v tt is a system supply for sign al termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 4. v dd q tracks with v dd ; v dd l tracks with v dd . 5. vssq = vssl = vss note: 1. r tt 1( eff ) and r tt 2( eff ) are determined by applying v ih ( ac ) and v il ( ac ) to pin under test separately, then measure current i(v ih ( ac )) and i(v il ( ac )) respectively. 2. measure voltage (vm) at tested pin with no load. table 17: recommended dc op erating conditions (sstl_18) all voltages referenced to v ss parameter symbol min nom max units notes supply voltage v dd 1.7 1.8 1.9 v 1, 5 v dd l supply voltage v dd l 1.7 1.8 1.9 v 4, 5 i/o supply voltage v dd q 1.7 1.8 1.9 v 4, 5 i/o reference voltage v ref ( dc ) 0.49 x v dd q 0.50 x v dd q 0.51 x v dd qv 2 i/o termination voltage (system) v tt v ref ( dc ) - 40 v ref ( dc )v ref ( dc ) + 40 mv 3 table 18: odt dc electrical characteristics all voltages referenced to v ss parameter symbol min nom max units notes r tt effective impedance value for 75 ? setting emr (a6, a2) = 0, 1 r tt 1( eff )60 75 90 ? 1 r tt effective impedance value for 150 ? setting emr (a6, a2) = 1, 0 r tt 2( eff ) 120 150 180 ? 1 deviation of vm with respect to v dd q/2 ? vm -6% 6% % 2 r tt eff () v ih ac () v il ac () ? iv ih ac () () iv il ac () () ? -------------------- --------------------- -------------------- = ? vm 2 vm v dd q ----------------- - 1 ? ?? ?? 100% =
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 76 ?2003 micron technology, inc. all rights reserved. input electrical characteris tics and operating conditions figure 63: single-end ed input si gnal levels note: numbers in diagram reflect nomimal values. table 19: input dc logic levels all voltages referenced to v ss parameter symbol min max units notes input high (logic 1) voltage v ih ( dc )v ref ( dc ) + 125 v dd q + 300 mv input low (logic 0) voltage v il ( dc ) -300 v ref ( dc ) - 125 mv table 20: input ac logic levels all voltages referenced to v ss parameter symbol min max units notes input high (logic 1) voltage v ih ( ac )v ref ( dc ) + 250 - mv input low (logic 0) voltage v il ( ac )? v ref ( dc ) - 250 mv 650mv 775mv 864mv 882mv 900mv 918mv 936mv 1,025mv 1,150mv v il (ac) v il (dc) v ref - ac noise v ref - dc error v ref + dc error v ref + ac noise v ih (dc) v ih (ac)
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 77 ?2003 micron technology, inc. all rights reserved. note: 1. v in (dc) specifies the allowable dc execution of each input of differential pair such as ck, ck#, dqs, dqs#, ldqs, ldqs#, udqs, udqs#, and rdqs, rdqs#. 2. v id (dc) specifies the input differential voltage | v tr - v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs, udqs, rdqs) level and v cp is the complementary input (such as ck#, dqs#, ldqs#, udqs#, rdqs#). the minimum value is equal to v ih (dc) - v il (dc). differential input signal levels are shown in figure 64. 3. v id (ac) specifies the input differential voltage | v tr - v cp | required for switching, where v tr is the true input (such as ck, dqs, ldqs, udqs, rdqs) level and v cp is the complementary input (such as ck#, dqs#, ldqs#, udqs#, rdqs#). the minimum value is equal to v ih (ac) - v il (ac) from table 20 on page 76. 4. the typical value of v ix (ac) is expected to be about 0.5 x v dd q of the transmitting device and v ix (ac) is expected to track variations in v dd q. v ix (ac) indicates the voltage at which differen tial input sign als must cross as shown in figure 64. 5. v mp ( dc ) specifies the input differen tial common mode voltage (v tr + v cp )/2 where v tr is the true input (ck, dqs) level and v cp is the complementary input (ck#, dqs#). v mp ( dc ) is expected to be about 0.5*v dd q. figure 64: differenti al input signal levels note: 1. this provides a minimum of 850mv to a ma ximum of 950mv and is expected to be v dd q/2. 2. tr and cp must cross in this region. 3. tr and cp must meet at least v id (dc) min when static and is centered around v mp (dc). 4. tr and cp must have a mi nimum 500mv peak-to-peak swing. 5. tr and cp may not be more positive than v dd q + 0.3v or more negative than v ss - 0.3v. 6. for ac operation, all dc clock re quirements must also be satisfied. 7. numbers in diagram reflect nominal values. 8. tr represents the ck, dqs, rdqs, ldqs and udqs signals; cp represents ck#, dqs#, rdqs#, ldqs# and udqs# signals. table 21: differential input logic levels all voltages referenced to v ss parameter symbol min max units notes dc input signal voltage v in (dc) -300 v dd q + 300 mv 1 dc differential input voltage v id (dc) 250 v dd q + 600 mv 2 ac differential input voltage v id (ac) 500 v dd q + 600 mv 3 ac differential cross-point voltage v ix (ac) 0.50 x v dd q - 175 0.50 x v dd q + 175 mv 4 input midpoint voltage v mp ( dc ) 850 950 mv 5 cp 8 tr 8 2.1 v @ v dd q=1.8v 2 3 v in(dc) max 5 v in(dc) min 5 4 - 0.30v 0.9v 1.075 v 0.725 v v id (ac) v id (dc) x 1 v mp (dc) v ix (ac) x
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 78 ?2003 micron technology, inc. all rights reserved. note: 1. all voltages referenced to v ss . 2. input waveform setup timing ( t is b ) is referenced from the inpu t signal crossi ng at the v ih(ac) level for a risi ng signal and v il ( dc ) for a falling signal applied to the de vice under test as shown in figure 73. 3. input waveform hold ( t ih b ) timing is referenced from the input signal cro ssing at the v il ( dc ) level for a rising signal and v ih ( dc ) for a falling signal appl ied to the device under test as shown in figure 73 4. input waveform setup timing ( t ds) and hold timing ( t dh) for single-ended data strobe is referenced from the crossing of dqs, udqs, or ldqs through the v ref level applied to the device under test as shown in figure 75. 5. input waveform setup timing ( t ds) and hold timing ( t dh) when differential data strobe is enabled is referenced from the crosspoint of dqs,dqs# or udqs,udqs# or ldqs,ldq s# as shown in figure 74. 6. input waveform ti ming is referenced to th e crossing point level (v ix ) of two input signals (v tr and v cp ) applied to the device under test, where v tr is the ?true? in put signal and v cp is the ?complementary? inpu t signal shown in figure 76. 7. see ?input slew rate derating? on page 79. table 22: ac input test conditions parameter symbol min max units notes input setup timing measurement reference level ba1-ba0, a0-a12, cs#, ra s#, cas#, we#, odt, dm, udm, ldm and cke v rs see note 2 1, 2, input hold timing meas urement reference level ba1-ba0, a0-a12, cs#, ra s#, cas#, we#, odt, dm, udm, ldm and cke v rh see note3 1, 3, input timing measurement refe rence level (single-ended) dqs for x4x8; udqs, ldqs for x16 v ref ( dc )v dd q*0.49 v dd q*0.51 v 1, 4 input timing measurement re ference level (differential) ck, ck# for x4,x8,x16 dqs, dqs# for x4,x8; rdqs, rdqs# for x8 udqs, udqs#, ldqs, ldqs# for x16 v rd v ix ( ac ) v 1, 5, 6
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 79 ?2003 micron technology, inc. all rights reserved. input slew rate derating for all input signals the total t is (setup time) and t ih (hold time) required is calc ulated by adding the data sheet t is(base) and t ih(base) value to the ? t is and ? t ih derating value respectively. example: t is (total setup time) = t is(base) + ? t is setup ( t is) nominal slew rate for a rising signal is defined as the slew rate be tween the last crossing of v ref ( dc ) and the first crossing of v ih ( ac )min. setup ( t is) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (d c ) and the first crossing of v il (a c ) max . if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref (d c ) to ac region?, use nominal slew rate for derating value (figure 65 on page 80) if the actual signal is later than the nomi nal slew rate line anywhere between shaded ?v ref (d c ) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (figure 66 on page 80) hold ( t ih) nominal slew rate for a rising signal is defined as the slew rate be tween the last crossing of v il ( dc ) max and the first crossing of v ref (d c ). hold ( t ih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih ( dc ) min and the first cr ossing of v ref (d c ). if the actual signal is always later than the nomina l slew rate line between shaded ?dc to v ref ( dc ) region?, use nominal slew rate for derating value (figure 67 on page 81) if the actual signal is earlier than the nominal slew rate line any- where between shaded ?dc to v ref ( dc ) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref ( dc ) level is used for derating value (figure 68 on page 81) although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih / il ( ac ) at the time of the rising clock tran- sition) a valid input signal is still required to complete the transition and reach v ih / il ( ac )). for slew rates in between the values listed in table 23, the derating valu es may obtained by linear interpolation. table 23: setup and hold time derating values ck,ck# differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns ? t is ? t ih ? t is ? t ih ? t is ? t ih units command/ address slew rate (v/ns) 4.0 +187 +94 +217 +124 +247 +154 ps 3.5 +179 +89 +209 +119 +239 +149 ps 3.0 +167 +83 +197 +113 +227 +143 ps 2.5 +150 +75 +180 +105 +210 +135 ps 2.0 +125 +45 +155 +75 +185 +105 ps 1.5 +83 +21 +113 +51 +143 +81 ps 1.0 0 0 +30 +30 +60 +60 ps 0.9 -11 -14 +19 +16 +49 +46 ps 0.8 -25 -31 +5 -1 +35 +29 ps 0.7 -43 -54 -13 -24 +17 +6 ps 0.6 -67 -83 -37 -53 -7 -23 ps 0.5 -110 -125 -80 -95 -50 -65 ps 0.4 -175 -188 -145 -158 -115 -128 ps 0.3 -285 -292 -255 -262 -225 -232 ps 0.25 -350 -375 -320 -345 -290 -315 ps 0.2 -525 -500 -495 -470 -465 -440 ps 0.15 -800 -708 -770 -678 -740 -648 ps 0.1 -1450 -1125 -1420 -1095 -1390 -1065 ps
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 80 ?2003 micron technology, inc. all rights reserved. figure 65: nominal slew rate for t is figure 66: tangent line for t is v ss ck ck tih tis tih setup slew rate setup slew rate rising signal falling signal delta tf delta tr v ref(dc) - vil(ac)max delta tf = vih(ac)min - v ref(dc) delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tis nominal slew rate nominal slew rate vref to ac region vref to ac region v ss ck ck tih tis tih setup slew rate rising signal delta tf delta tr tangent line[vih(ac)min - v ref(dc) ] delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tis tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 81 ?2003 micron technology, inc. all rights reserved. figure 67: nominal slew rate for t ih figure 68: tangent line for t ih v ss ck ck tih tis tih delta tr delta tf v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tis nominal slew rate nominal slew rate dc to v ref region dc to v ref region v ss ck ck tih tis tih hold slew rate delta tf delta tr tangent line [ vih(dc)min - v ref(dc) ] delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tis tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] delta tr = rising signal
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 82 ?2003 micron technology, inc. all rights reserved. data slew rating note: 1. for all input signals the total t ds (setup time) and t dh (hold time) required is calculat ed by adding the datasheet value to the derating value listed in table 24. 2. setup ( t ds) nominal slew rate for a rising signal is define d as the slew rate between the last crossing of v ref(dc) and the first crossing of vih(ac)min. setup ( t ds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier th an the nomina l slew rate line between shaded ?v ref(dc) to ac region?, use nominal slew rate for derati ng value (see figure 69) if the actual signal is later than the nominal slew rate line anywhere between shaded ?v ref(dc) to ac region?, the slew rate of a tangent line to the actual signal fro m the ac level to dc level is us ed for derating value (see figure 70) 3. hold ( t dh) nominal slew rate for a rising sign al is defined as the slew rate betwee n the last crossing of vil(dc)max and the first crossing of v ref(dc) . hold ( t dh) nominal slew rate for a fa lling signal is defined as th e slew rate between the last crossing of vih(dc)min and the first crossing of v ref(dc) . if the actual signal is always la ter than the nominal slew rate line between shaded ?dc level to v ref(dc) region?, use nominal slew rate for derating value (see figu re 71) if the actual signal is earlier than the nomina l slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref(dc) level is used for derating value (see figure 72) 4. although for slow slew rates the total setup time might be negative (i.e. a va lid input signal will not have reached v ih/ il (ac) at the time of the rising clock trans ition) a valid input signal is still requ ired to complete th e transition and reach v ih/il (ac). 5. for slew rates in between the values listed in table 24, the derating values may obtain ed by linear interpolation. 6. these values are typically not subjec t to production test. they are veri fied by design and characterization. table 24: t ds, t dh derating values note 1; all units in ps dqs,dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns ? t ds ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h ? t d s ? t d h dq slew rate v/ns 2.0125451254512545------------ 1.58321832183219533---------- 1.000000012122424-------- 0.9---11-14-11-141-213102522------ 0.8 - - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - - 0.7 - - - - - - -31 -42 -19 -30 -7 -18 5 -6 17 6 - - 0.6 - - - - - - - - -43 -59 -31 -47 -19 -35 -7 -23 5 -11 0.5 - - - - - - - - - - -74 -89 -62 -77 -50 -65 -38 -53 0.4----- - -------127-140-115-128-103-116
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 83 ?2003 micron technology, inc. all rights reserved. figure 69: nominal slew rate for t ds figure 70: tangent line for t ds v ss dqs note1 dqs note1 tdh tds tdh setup slew rate setup slew rate rising signal falling signal delta tf delta tr v ref(dc) - vil(ac)max delta tf = vih(ac)min - v ref(dc) delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds nominal slew rate nominal slew rate vref to ac region vref to ac region note1 dqs, dqs# signals must be monotonic between vil(dc)max and vih(dc)min. v ss dqs note1 dqs note1 tdh tds tdh setup slew rate setup slew rate rising signal falling signal delta tf delta tr tangent line[ v ref(dc) - vil(ac)max] delta tf = tangent line[vih(ac)min - v ref(dc) ] delta tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line note1 dqs, dqs# signals must be monotonic between vil(dc)max and vih(dc)min.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 84 ?2003 micron technology, inc. all rights reserved. figure 71: nominal slew rate for t dh figure 72: tangent line for t dh v ss dqs note1 dqs note1 tdh tds tdh hold slew rate hold slew rate falling signal rising signal delta tr delta tf v ref(dc) - vil(dc)max delta tr = vih(dc)min - v ref(dc) delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds nominal slew rate nominal slew rate dc to v ref region dc to v ref region note1 dqs, dqs# signals must be monotonic between vil(dc)max and vih(dc)min. v ss dqs note1 dqs note1 tdh tds tdh hold slew rate delta tf delta tr tangent line [ vih(dc)min - v ref(dc) ] delta tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tds tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] delta tr = rising signal note1 dqs, dqs# signals must be monotonic between vil(dc)max and vih(dc)min.
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 85 ?2003 micron technology, inc. all rights reserved. figure 73: ac input test si gnal waveform command/address pins figure 74: ac input test signal wavef orm for data with dq s,dqs# (differential) v ref (dc) v il (dc) ma x v il (ac) ma x v ss q v ih (dc) m in v ih (ac) mi n v dd q v swing (max) t is a l ogic levels v ref levels t ih a t is a t ih a t is b t ih b t is b t ih b ck# ck v ref (dc) v il (dc) ma x v il (ac) ma x v ss q v ih (dc) m in v ih (ac) mi n v dd q v swing (max) dqs# dqs t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b l ogic levels v ref levels
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 86 ?2003 micron technology, inc. all rights reserved. figure 75: ac input test signal w aveform for data with dqs (single-ended) figure 76: ac input test si gnal waveform (differential) v ref (dc) v il (dc) ma x v il (ac) ma x v ss q v ih (dc) m in v ih (ac) mi n v dd q v swing (max) dqs v ref l ogic levels v ref levels v ref levels t ds a t dh a t ds a t dh a t ds b t dh b t ds b t dh b v tr v swing v cp v dd q v ss q v ix crossing point
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 87 ?2003 micron technology, inc. all rights reserved. power and ground clamp characteristics power and ground clamps are provided on the fol- lowing input-only pins: ba1-ba0, a0-a12, cs#, ras#, cas#, we#, odt, and cke. figure 77: input clamp characteristics table 25: input clamp characteristics voltage across clamp (v) minimum power clamp current (ma) minimum ground clamp current (ma) 0.0 0.0 0.0 0.1 0.0 0.0 0.2 0.0 0.0 0.3 0.0 0.0 0.4 0.0 0.0 0.5 0.0 0.0 0.6 0.0 0.0 0.7 0.0 0.0 0.8 0.1 0.1 0.9 1.0 1.0 1.0 2.5 2.5 1.1 4.7 4.7 1.2 6.8 6.8 1.3 9.1 9.1 1.4 11.0 11.0 1.5 13.5 13.5 1.6 16.0 16.0 1.7 18.2 18.2 1.8 21.0 21.0 0.0 5.0 10.0 15.0 20.0 25.0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 voltage across clamp (v) minimum clamp current (ma)
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 88 ?2003 micron technology, inc. all rights reserved. ac overshoot/undershoot specification figure 78: overshoot figure 79: undershoot table 26: address and control pins applies to ba1-ba0, a0-a12, cs #, ras#, cas#, we#, cke, odt parameter specification -5e -37e maximum peak amplitude allowed for overshoot area (see figure 78) 0.9v 0.9v maximum peak amplitude allowed for undershoot area (see figure 79) 0.9v 0.9v maximum overshoot area above v dd (see figure 78) 0.75v-ns 0.56v-ns maximum undershoot area below v ss (see figure 79) 0.75v-ns 0.56v-ns table 27: clock, data, strobe, and mask pins applies to dq0?dqxx, dqs, dqs#, rdqs, rdqs #, udqs, udqs#, ldqs, ldqs#, dm, udm, ldm parameter specification -5e -37e maximum peak amplitude allowed for overshoot area (see figure 78) 0.9v 0.9v maximum peak amplitude allowed for undershoot area (see figure 78) 0.9v 0.9v maximum overshoot area above v dd q (see figure 78) 0.38v-ns 0.28v-ns maximum undershoot area below v ss q (see figure 79) 0.38v-ns 0.28v-ns overshoot area maximum amplitude v dd / v dd q v ss/ v ss q volts time (ns) (v) undershoot area maximum amplitude v ss/ v ss q volts time (ns) (v)
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 89 ?2003 micron technology, inc. all rights reserved. output electrical characteris tics and operating conditions note: 1. the typical value of v ox (ac) is expected to be about 0.5 x v dd q of the transmitting device and v ox (ac) is expected to track variations in v dd q. v ox (ac) indicates the voltage at which di fferential output signals must cross. figure 80: differential output signal levels table 28: differential ac output parameters parameter symbol min max units notes ac differential cross-point voltage v ox ( ac ) 0.50 x v dd q - 125 0.50 x v dd q + 125 mv 1 ac differential voltage swing v swing 1.0 mv v tr v swing v cp v dd q v ss q v ox crossing point
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 90 ?2003 micron technology, inc. all rights reserved. note: 1. for i oh (dc); v dd q = 1.7v, v out = 1420mv. (v out - v dd q)/i oh must be less than 21 ? for values of v out between v dd q and v dd q - 280mv. 2. for i ol (dc); v dd q = 1.7v, v out = 280mv. v out /i ol must be less than 21 ? for values of v out between 0v and 280mv. 3. the dc value of v ref applied to the receiving device is set to v tt . 4. the values of i oh (dc) and i ol (dc) are based on the conditions given in note s 1 and 2. they are used to test device drive current capability to ensure v ih (min) plus a noise margin and v il (max) minus a noise marg in are delivered to an sstl_18 receiver. the actual current values are derived by sh ifting the desired driver oper ating point (see output iv curves) along a 21 ? load line to define a convenie nt driver current for measurement. note: 1. absolute specifications: 0c t case +85c ; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v. 2. impedance measurement condition for output source dc current: v dd q = 1.7v; v out = 1420mv; (v out - v dd q)/i oh must be less than 23.4 ? for values of v out between v dd q and v dd q - 280mv. impedance measurement condition for output sink dc current: v dd q = 1.7v; v out = 280mv; v out /i ol must be less than 23.4 ? for values of v out between 0v and 280mv. 3. mismatch is absolute value between pull-up and pull-dow n, both are measured at same temperature and voltage. 4. output slew rate for falling and rising edges is measured between v tt - 250mv and v tt + 250mv for single ended sig- nals. for differential signals (e.g. dqs - dqs#) output slew rate is measured between dqs - dqs# = -500mv and dqs# - dqs = +500mv. output slew rate is guaranteed by design, but is not ne cessarily tested on each device. 5. the absolute value of the slew rate as measured from v il (dc)max to v ih (dc) min is equal to or greater than the slew rate as measured from v il (ac) max to v ih (ac) min. this is guaranteed by design and characterization. figure 81: output slew rate load table 29: output dc current drive parameter symbol value units notes output minimum source dc current i oh -13.4 ma 1,3,4 output minimum sink dc current i ol 13.4 ma 2,3,4 table 30: output characteristics parameter symbol min nom max units notes output impedance 12.6 18 23.4 ? s 1,2 pull-up and pull -down mismatch 04 ? s 1,2,3 output slew rate 1.5 5 v/ns 1,4,5 output (v out ) reference point 25 ? v tt = v dd q/2
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 91 ?2003 micron technology, inc. all rights reserved. full strength pull-down driver characteristics figure 82: full strength pull-down characteristics pull-down characteristics 0.00 20.00 40.00 60.00 80.00 100.00 120.00 0.0 0.5 1.0 1.5 vout (v) iout (ma) table 31: pulldown current (ma) voltage (v) minimum nominal maximum 0.0 0.00 0.00 0.00 0.1 4.3 5.63 7.95 0.2 8.6 11.3 15.90 0.3 12.9 16.52 23.85 0.4 16.9 22.19 31.80 0.5 20.4 27.59 39.75 0.6 23.28 32.39 47.70 0.7 25.44 36.45 55.55 0.8 26.79 40.38 62.95 0.9 27.67 44.01 69.55 1.0 28.38 47.01 75.35 1.1 28.96 49.63 80.35 1.2 29.46 51.71 84.55 1.3 29.90 53.32 87.95 1.4 30.29 54.9 90.70 1.5 30.65 56.03 93.00 1.6 30.98 57.07 95.05 1.7 31.31 58.16 97.05 1.8 31.64 59.27 99.05 1.9 31.96 60.35 101.05
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 92 ?2003 micron technology, inc. all rights reserved. full strength pull-up driver characteristics figure 83: full streng th pull-up characteristics pull-up characteristics -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 0.0 0.5 1.0 1.5 vddq - vout (v) iout (ma) table 32: pull-up current (ma) voltage (v) minimum nominal maximum 0.0 0.00 0.00 -0.00 0.1 -4.3 -5.63 -7.95 0.2 -8.6 -11.3 -15.90 0.3 -12.9 -16.52 -23.85 0.4 -16.9 -22.19 -31.80 0.5 -20.4 -27.59 -39.75 0.6 -23.28 -32.39 -47.70 0.7 -25.44 -36.45 -55.55 0.8 -26.79 -40.38 -62.95 0.9 -27.67 -44.01 -69.55 1.0 -28.38 -47.01 -75.35 1.1 -28.96 -49.63 -80.35 1.2 -29.46 -51.71 -84.55 1.3 -29.90 -53.32 -87.95 1.4 -30.29 -54.90 -90.70 1.5 -30.65 -56.03 -93.00 1.6 -30.98 -57.07 -95.05 1.7 -31.31 -58.16 -97.05 1.8 -31.64 -59.27 -99.05 1.9 -31.96 -60.35 -101.05
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 93 ?2003 micron technology, inc. all rights reserved. fbga package capacitance note: 1. this parameter is sampled. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v ref = v ss , f = 100 mhz, t case = 25c, v out (dc) = v dd q/2, v out (peak to peak) = 0.1v. dm input is grouped with i/o pi ns, reflecting the fact that they are matched in load- ing. 2. the input capacitance per pin group will not differ by more than this maximum amount for any given device. 3. the i/o capacitance per dqs and dq by te/group will not differ by more than this maximum amount for any given device. table 33: input capacitance parameter symbol min max units notes input capacitance: ck, ck# cck 1.0 2.0 pf 1 delta input capacitance: ck, ck# cdck ? 0.25 pf 2 input capacitance: ba1- ba0, a0-a12, cs#, ras#, cas#, we#, cke, odt ci 1.0 2.0 pf 1 delta input capacitance: ba1-ba0, a0-a12, cs#, ras#, cas#, we#, cke, odt cdi ? 0.25 pf 2 input/output capacitance: dqs, dqs, dm, nf cio 2.5 4.0 pf 1 delta input/output capaci tance: dqs, dqs, dm, nf cdio ? 0.5 pf 3
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 94 ?2003 micron technology, inc. all rights reserved. i dd specifications and conditions table 34: ddr2 i dd specifications and conditions notes: 1?5; notes appear on page 10. parameter/condition symbol config -37e -5e units operating one bank active-precharge current; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, cs# is high between valid comma nds; address bus inputs are switching; data bus inputs are switching. i dd 0 x4, x8 80 75 ma x16 80 75 operating one bank active-read-precharge current; iout = 0ma; bl = 4, cl = cl(i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid co mmands; address bus inputs are switching; data pattern is same as i dd 4w. i dd 1 x4, x8 90 85 ma x16 90 85 precharge power-down current ; all banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. i dd 2p x4, x8, x16 5 5 ma precharge quiet standby current ; all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are floating. i dd 2q x4, x8 35 25 ma x16 35 25 precharge standby current ; all banks idle; t ck = t ck (i dd ); cke is high, cs# is high; other control and address bus inputs ar e switching; data bus inputs are switching. i dd 2n x4, x8 35 30 ma x16 35 30 active power-down current ; all banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating. i dd 3p fast pdn exit mr[12] = 0 25 20 ma slow pdn exit mr[12] = 1 66 active standby current ; all banks open; t ck = t ck(i dd ), t ras = t ras max (i dd ), t rp = t rp(i dd ); cke is high, cs# is high between valid commands; other control and address bus inputs are swi tching; data bus inputs are switching. i dd 3n x4, x8 40 30 ma x16 40 30 operating burst write current ; all banks open, continuous bur st writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid comma nds; address bus inputs are switching; data bus inputs are switching. i dd 4w x4, x8 160 125 ma x16 180 140 operating burst read current ; all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs ar e switching; data bu s inputs are switching. i dd 4r x4, x8 150 115 ma x16 160 120 burst refresh current ; t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, cs# is high between vali d commands; other control and address bus inputs are switching; data bus inputs are switching. i dd 5 x4, x8 170 165 ma x16 170 165 self refresh current ; ck and ck# at 0v; cke 0.2v; other control an d address bus inputs are floating; data bus inputs are floating. i dd 6 x4, x8, x16 5 5 ma
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 95 ?2003 micron technology, inc. all rights reserved. note: 1. i dd specifications are tested after the device is properly initialized. 0c t case 85c. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v dd l= +1.8v 0.1v, v ref =v dd q/2. 2. input slew rate is specified by ac parametric test conditions. 3. i dd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs#, rdqs, rdqs#, ldqs, ldqs#, udqs, and udqs#. i dd values must be met with all combinations of emr bits 10 and 11. 5. definitions for i dd conditions: low is defined as v in v il (ac) (max). high is defined as v in v ih (ac) (min). stable is defined as inputs stable at a high or low level. floating is defined as inputs at v ref = v dd q/2. switching is defined as inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals. switching is defined as inputs changing between high and low every other data transfer (once per clock) for dq signals not includ ing masks or strobes. operating bank interleave read current ; all bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd )-1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc(i dd ), t rrd = t rrd(i dd ), t rcd = t rcd(i dd ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching; see i dd 7 conditions for detail. i dd 7 x4, x8 240 230 ma x16 240 230 table 34: ddr2 i dd specifications and conditions (continued) notes: 1?5; notes appear on page 10. parameter/condition symbol config -37e -5e units table 35: general i dd parameters i dd parameter -37e -5e units cl (i dd ) 43 t ck t rcd (i dd ) 15 15 ns t rc (i dd ) 60 55 ns t rrd (i dd ) - x4/x8 7.5 7.5 ns t rrd (i dd ) - x16 10 10 ns t ck (i dd ) 3.75 5 ns t ras min (i dd ) 45 40 ns t ras max (i dd ) 70,000 70,000 ns t rp (i dd ) 15 15 ns t rfc (i dd ) 127.5 127.5 ns
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 96 ?2003 micron technology, inc. all rights reserved. i dd 7 conditions the detailed timings are shown below for i dd 7. changes will be required if timing parameter changes are made to the specification. note: 1. legend: a = active; ra = read auto precharge; d = deselect. 2. all banks are being in terleaved at minimum t rc (i dd ) without violating t rrd (i dd ) using a burst length of 4. 3. control and address bus inputs are stable during deselects. 4. i out = 0ma. table 36: i dd 7 timing patterns all bank interleav e read operation speed grade idd7 timing patterns for x4/x8/x16 -5e a0 ra0 a1 ra1 a2 ra2 a3 ra3 d d d d -37e a0 ra0 d a1 ra1 d a2 ra2 d a3 ra3 d d d d d
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 97 ?2003 micron technology, inc. all rights reserved. table 37: ac operating co nditions (sheet 1 of 4) notes: 1?5; notes appear on page 27; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -37e -5e parameter symbol min max min max units notes clock clock cycle time cl = 4 t ck (4) 3,750 8,000 5,000 8,000 ps 16, 25 cl = 3 t ck (3) 5,000 8,000 5,000 8,000 ps 16, 25 ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 19 ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 19 half clock period t hp min ( t ch, t cl) min ( t ch, t cl) ps 20 clock jitter t jit tbd tbd tbd tbd ps 18 data dq output access time from ck/ck# t ac -500 +500 -600 +600 ps data-out high-impedance window from ck/ck# t hz t ac max t ac max ps 8, 9 data-out low-impedance window from ck/ck# t lz t ac min t ac max t ac min t ac max ps 8, 10 dq and dm input setup time relative to dqs t ds a 350 400 ps 7, 15, 22 dq and dm input hold time relative to dqs t dh a 350 400 ps 7, 15, 22 dq and dm input setup time relative to dqs t ds b 100 150 ps 7, 15, 22 dq and dm input hold time relative to dqs t dh b 225 275 ps 7, 15, 22 dq and dm input pulse width (for each input) t dipw 0.35 0.35 t ck data hold skew factor t qhs 400 450 ps dq?dqs hold, dqs to first dq to go nonvalid, per access t qh t hp - t qhs t hp - t qhs ps 15, 17 data valid output window (dvw) t dvw t qh - t dqsq t qh - t dqsq ns 15, 17
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 98 ?2003 micron technology, inc. all rights reserved. data strobe dqs input high pulse width t dqsh 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck -450 +450 -500 +500 ps dqs falling edge to ck rising ? setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising ? hold time t dsh 0.2 0.2 t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq 300 350 ps 15, 17 dqs read preamble t rpre 0.9 1.1 0.9 1.1 t ck 36 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck 36 dqs write preamble setup time t wpres 0 0 ps 12, 13 dqs write preamble t wpre 0.25 0.25 t ck dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 11 write command to first dqs latching transition t dqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 t ck table 37: ac operating co nditions (sheet 2 of 4) notes: 1?5; notes appear on page 27; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -37e -5e parameter symbol min max min max units notes
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 99 ?2003 micron technology, inc. all rights reserved. command and address address and control input pulse width for each input t ipw 0.6 0.6 t ck address and control input setup time t is a 500 600 6, 22 address and control input hold time t ih a 500 600 6, 22 address and control input setup time t is b 250 350 6, 22 address and control input hold time t ih b 375 475 6, 22 cas# to cas# command delay t ccd 22 t ck active to active (same bank) command t rc 55 55 ns 34 active bank a to active bank b command t rrd (x4, x8) 7.5 7.5 ns 28 t rrd (x16) 10 10 ns 28 active to read or write delay t rcd 15 15 ns four bank activate period t faw (x4, x8) 37.5 37.5 ns 31 four bank activate period t faw (x16) 50 50 ns 31 active to precharge command t ras 40 70,000 40 70,000 ns 21, 34 internal read to precharge command delay t rtp 7.5 7.5 ns 24, 28 write recovery time t wr 15 15 ns 28 auto precharge write recovery + precharge time t dal t wr + t rp t wr + t rp ns 23 internal write to read command delay t wtr 7.5 10 ns 28 precharge command period t rp 15 15 ns 32 precharge all command period t rpa t rp + t ck t rp + t ck ns 32 load mode command cycle time t mrd 22 t ck cke low to ck,ck# uncertainty t delay 4.375 4.375 5.83 5.83 ns 29 refresh refresh to active or refresh to refresh command interval t rfc 75 70,000 75 70,000 ns 14 average periodic refresh interval t refi 7.8 7.8 s 14 table 37: ac operating co nditions (sheet 3 of 4) notes: 1?5; notes appear on page 27; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -37e -5e parameter symbol min max min max units notes
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 100 ?2003 micron technology, inc. all rights reserved. self refresh exit self refresh to non-read command t xsnr t rfc (min) + 10 t rfc (min) + 10 ns exit self refresh to read command t xsrd 200 200 t ck exit self refresh timing reference t isxr 250 350 ps 6, 30 odt odt turn-on delay t aond 2222 t ck odt turn-on t aon t ac (min) t ac (max) + 1,000 t ac (min) t ac (max) + 1000 ps 26 odt turn-off delay t aofd 2.5 2.5 2.5 2.5 t ck odt turn-off t aof t ac (min) t ac (max) + 600 t ac (min) t ac (max) + 600 ps 27 odt turn-on (power-down mode) t aonpd t ac (min) + 2000 2 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2 x t ck + t ac (max) + 1000 ps odt turn-off (power-down mode) t aofpd t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 t ac (min) + 2,000 2.5 x t ck + t ac (max) + 1,000 ps odt to power-down entry latency t anpd 33 t ck odt power-down exit latency t axpd 88 t ck power-down exit active power-down to read command, mr[bit12=0] t xard 22tck exit active power-down to read command, mr[bit12=1] t xards 6 - al 6 - al t ck exit precharge power-down to any non-read command. t xp 22 t ck exit precharge power-down to read command. t xprd 6 - al 6 - al t ck cke minimum hi gh/low time t cke 33 t ck 35 table 37: ac operating co nditions (sheet 4 of 4) notes: 1?5; notes appear on page 27; 0c t case +85c; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics -37e -5e parameter symbol min max min max units notes
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 101 ?2003 micron technology, inc. all rights reserved. notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device oper ation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.0v in the test environment and parame- ter specifications are guar anteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test the device is 1.0v/ns for signals in the range between v il (ac) and v ih (ac). slew rates less than 1.0v/ns require the timing parameters to be derated as specified. 5. the ac and dc input level specifications are as defined in the sstl_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. command/address minimum input slew rate is at 1.0v/ns. command/address input timing must be derated if the slew rate is not 1.0v/ns. this is eas- ily accommodated using t is b and the setup and hold time derating values table. t is timing ( t is b ) is referenced from v ih ( ac ) for a rising signal and v il ( ac ) for a falling signal. t ih timing ( t ih b ) is refer- enced from v ih ( ac ) for a rising signal and v il ( dc ) for a falling signal. the timing table also lists the t is b and t ih b values for a 1.0v/n s slew rate; these are the ?base? values. 7. data minimum input slew rate is at 1.0v/ns. data input timing must be derated if the slew rate is not 1.0v/ns. this is easily accommodated if the tim- ing is referenced from the logic trip points. t ds timing ( t ds b ) is referenced from v ih (ac) for a ris- ing signal and v il (ac) for a falling signal. t ih tim- ing ( t ih b ) is referenced from v ih (dc) for a rising signal and v il ( dc ) for a falling signal. the timing table lists the t ds b and t dh b values for a 1.0v/ns slew rate. if the dqs/dqs# differential strobe feature is not enabled, timing is no lo nger referenced to the crosspoint of dqs/dqs#. data timing is now ref- erenced to v ref , provided the dqs slew rate is not less than 1.0v/ns. if the dqs slew rate is less than 1.0v/ns, then data timing is now referenced to v ih ( ac ) for a rising dqs and v il ( dc ) for a falling dqs. 8. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenc ed to a specific voltage level, but specify when the device output is no longer driving ( t hz) or begins driving ( t lz). 9. this maximum value is derived from the refer- enced test load. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 10. t lz (min) will prevail over a t dqsck (min) + t rpre (max) condition. 11. the intent of the don?t care state after completion of the postamble is the dqs-driven signal should either be high, low or high-z and that any signal transition within the input switching region must follow valid input requirements. that is if dqs transitions high (above v ih dc(min) then it must not transition low (below v ih (dc) prior to t dqsh(min). 12. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 13. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss. 14. the refresh period is 64ms. this equates to an average refresh rate of 7.8125s. however, a refresh command must be asserted at least once every 70.3s or t rfc (max). to ensure all rows of all banks are properly refreshed, 8192 refresh commands must be issued every 64ms. 15. referenced to each output group: x4 = dqs with dq0-dq3; x8 = dqs with dq0?dq7; x16 = ldqs with dq0?dq7; and udqs with dq8?dq15. 16. ck and ck# input slew rate must be 1v/ns ( 2 v/ns if measured differentially). 17. the data valid window is derived by achieving other specifications - t hp. ( t ck/2), t dqsq, and t qh( t qh= t hp- t qhs). the data valid window der- ates in direct proportion to the clock duty cycle and a practical data valid window can be derived. 18. t jit specification is currently tbd. output (v out ) reference point 25 ? v tt = v dd q/2
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 102 ?2003 micron technology, inc. all rights reserved. 19. min( t cl, t ch) refers to the smaller of the actual clock low time and the ac tual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t cl and t ch). for example, t cl and t ch are = 50 percent of the period, less the half period jitter [ t jit(hp)] of the clock source, and less the half period jitter due to cross talk [ t jit(cross talk)] into the clock traces. 20. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs. 21. reads and writes with auto precharge are allowed to be issued before t ras (min) is satisfied since t ras lockout feature is supported in ddr2 sdram. 22. v il /v ih ddr2 overshoot/undershoot. see ?ac overshoot/undershoot spec ification? on page 87. 23. t dal = (nwr) + ( t rp/ t ck): for each of the terms above, if not already an integer, round to the next highest integer. t ck refers to the application clock period; nwr refers to the t wr parameter stored in the mr[11,10,9]. example: for -37e at t ck = 3.75 ns with t wr programmed to four clocks. t dal = 4 + (15 ns/3.75 ns) clocks = 4 +(4) clocks = 8 clocks. 24. the minimum read to internal precharge time. this parameter is only applicable when t rtp/(2* t ck) > 1. if t rtp/(2* t ck) 1, then equa- tion al + bl/2 applies. notwithstanding, t ras (min) has to be satisfied as well. the ddr2 sdram will automatically delay the internal pre- charge command until t ras (min) has been satisfied. 25. operating frequency is only allowed to change during self refresh mode (see ?self refresh? on page 34), precharge power-down mode (see ?power-down mode? on page 37), and system reset condition (see ?reset function (cke low anytime)? on page 8. 26. odt turn-on time t aon (min) is when the device leaves high impedance and odt resistance begins to turn on. odt turn-on time t aon (max) is when the odt resistance is fully on. both are measured from t aond. 27. odt turn-off time t aof (min) is when the device starts to turn off odt resistance. odt turn off time t aof (max) is when the bus is in high impedance. both are measured from t aofd. 28. this parameter has a two clock minimum require- ment at any t ck. 29. t delay is calculated from t is + t ck + t ih so that cke registration low is guaranteed prior to ck, ck# being removed in a system reset condition. ?reset function (cke low anytime)? on page 8. 30. t isxr is equal to t is and is used for cke setup time during self refresh exit shown in figure 31 on page 36. 31. no more than 4 bank active commands may be issued in a given t faw(min) period. t rrd(min) restriction still applies. the t faw(min) parameter applies to all 8 bank ddr2 devices, regardless of the number of banks al ready open or closed. 32. trpa timing applies when the precharge(all) command is issued, regardless of the number of banks already open or cl osed. if a single-bank precharge command is issued, t rp timing applies. t rpa(min) applies to all 8-bank ddr2 devices. 33. value is minimum pulse width, not the number of clock registrations. 34. applicable to read cycles only. write cycles gener- ally require additional time due to write recovery time ( t wr) during auto precharge. 35. t cke (min) of 3 clocks means cke must be regis- tered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not tran- sition from its valid level during the time period of t is + 2 * t ck + t ih. 36. this parameter is not referenced to a specific volt- age level, but specified whwen the device output is no longer driving ( t rpst) or beginning to drive ( t rpre).
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 103 ?2003 micron technology, inc. all rights reserved. figure 84: package drawin g 60-ball (8mm x12mm) fbga note: all dimensions ar e in millimeters. ball a1 id 1.3 max mold compound: epoxy novolac substrate: plastic laminate solder ball material: 62% sn, 36% pb, 2% ag or 95.5% sn, 3% ag, 0.5% cu solder ball pad: ? .33mm ball a9 0.80 typ 8.00 0.10 4.00 0.05 3.20 0.05 4.00 0.05 0.850 0.05 0.155 0.013 seating plane c 8.00 6.40 1.80 0.05 ctr 0.10 c 60x ? 0.45 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ? 0.42 c l 12.00 0.10 ball a1 ball a1 id 0.80 typ 6.00 0.05 c l
256mb: x4, x8, x16 ddr2 sdram 09005aef80b12a05 micron technology, inc., reserves the right to change products or specifications without notice. 256mb_ddr2_2.fm - rev. d 7/04 en 104 ?2003 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. figure 85: package drawin g 84-ball (8mm x14mm) fbga note: all dimensions ar e in millimeters. data sheet designation this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for prod uction devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ball #1 id seating plane 0.850 0.05 1.80 0.05 ctr 0.155 0.013 0.10 c c 1.3 max mold compound: epoxy novolac substrate: plastic laminate solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3% ag, 0.5% cu solder ball pad: ? 0.33mm c l c l 3.20 0.05 4.00 0.05 8.00 0.10 ball a1 id 11.20 5.60 0.05 ball a9 ball a1 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ?0.42 84x ?0.45 14.00 0.10 7.00 0.05 0.80 typ 0.80 typ 6.40

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